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Collected data for both common-source and common-gate amplifiers is presented in this paper. Characterizations of the two amplifier circuits using metal-ferroelectric-semiconductor field effect transistors (MFSFETs) are developed with wider input frequency ranges and varying device sizes compared to earlier characterizations. The effects of the ferroelectric layer's capacitance and variation load, quiescent point, or input signal on each circuit are discussed. Comparisons between the MFSFET and MOSFET circuit operation and performance are discussed at length as well as applications and advantages for the MFSFETs.

The ferroelectric transistor (FeFET) provides unique characteristics of memory circuits due to its hysteresis effects. This paper examines the design considerations of a 1T-1C dynamic random-access memory (DRAM) cell using a ferroelectric transistor. The research investigates the effects of the FeFET on the DRAM cell while modifying design parameters which are controlled by the circuit designer. Parameters include channel width and length and write-word-line (WWL) voltage. Experimental data will be taken for different circuit configurations. Comparisons will be made to similar circuits that utilize only metal-oxide-semiconductor field effect transistors (MOSFETs).

Dynamic random-access memory (DRAM) cells offer advantages over static random-access memory (SRAM) cells due to their reduced size and relaxed constraints on device sizing ratios. In this paper, the usage of a metal-ferroelectric-semiconductor field effect transistor (MFSFET) in a three-transistor dynamic random-access memory (DRAM) cell is examined, in order to determine the effects caused by its hysteresis properties. Combinations of metal-oxide-semiconductor field effect transistors (MOSFETs) and MFSFETs are explored, along with implementations consisting only of MFSFETs. The effects seen in these circuit configurations will be compared to configurations using only MOSFETs. Experimental data will be presented, showing the effect of varying parameters of the devices and circuit, such as channel length and width, input voltage waveforms, load devices, and capacitance. Particularly, attention will be given to the application of waveforms containing negative voltages to the gates of the transistors.

Mathematical models of the common-source and common-gate amplifiers using metal-ferroelectric- semiconductor field effect transistors (MOSFETs) are developed in this paper. The models are compared against data collected with MOSFETs of varying channel lengths and widths, and circuit parameters such as biasing conditions are varied as well. Considerations are made for the capacitance formed by the ferroelectric layer present between the gate and substrate of the transistors. Comparisons between the modeled and measured data are presented in depth as well as differences and advantages as compared to the performance of each circuit using a MOSFET.

In this paper, empirical data describing the channel resistance and polarization of several metal-ferroelectric-semiconductor field-effect transistors (MFSFETs) is presented. Various channel length and width transistors were used to describe the channel resistance under various biasing conditions and in both positive and negative polarization states. The presented results and analysis provide insight into the switching speed between polarization states as well as the timing and retention constraints for a given set of device dimensions. This is of particular value when considering circuit designs that utilize MFSFETs, especially digital memory circuits.

The implementation of a non-volatile latch circuit developed with a metal–ferroelectric–semiconductor field-effect transistor is presented. The circuit contains two inverter stages in order to create and rectify the desired waveform. The hysteresis properties of the ferroelectric transistor allow it to retain a polarisation state after an applied voltage at the gate is removed. This circuit has reduced power requirements because a constant power supply is not needed at all times; instead, a voltage is only needed at the gate of the ferroelectric transistor when storing a value, and the other components only need a power supply when reading the stored value from the circuit. The circuit is less complex than similar non-volatile latches because only a single ferroelectric transistor is used and fewer overall transistors may be used. It also has the advantage of being radiation-hardened for space applications.

I-V characteristics for FeFET different than that of MOSFET Ferroelectric layer features hysteresis trend whereas MOSFET behaves same for both increasing and decreasing VGS FeFET I-V characteristics doesn't show dependence on VDS A Transistor with different channel length and width as well as various resistance and input voltages give different results As resistance values increased, the magnitude of the drain current decreased.

The SRAM cell circuit is a standard for volatile data storage. When utilizing one or more ferroelectric transistors, the hysteresis characteristics give unique properties to the SRAM circuit, providing for investigation into the development of a nonvolatile memory cell. This paper discusses various formations of the SRAM circuit, using ferroelectric transistors, n-channel and p-channel MOSFETs, and resistive loads. With varied source and supply voltages, the effects on the timing and retention characteristics are investigated, including retention times of up to 24 hours.

The inverter is one of the most fundamental building blocks of digital logic, and it can be used as the foundation for understanding more complex logic gates and circuits. This paper presents the characteristics of an inverter circuit using a ferroelectric field-effect transistor. The voltage transfer characteristics are analyzed with respect to varying parameters such as supply voltage, input voltage, and load resistance. The effects of the ferroelectric layer between the gate and semiconductor are examined, and comparisons are made between the inverters using ferroelectric transistors and those using traditional MOSFETs.

This paper presents the switching characteristics of an inverter circuit using a ferroelectric field effect transistor, FeFET. The propagation delay time characteristics, phl and plh are presented along with the output voltage rise and fall times, rise and fall. The propagation delay is the time-delay between the V50% transitions of the input and output voltages. The rise and fall times are the times required for the output voltages to transition between the voltage levels V10% and V90%. Comparisons are made between the MOSFET inverter and the ferroelectric transistor inverter.