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3,156 results on '"Clock signal"'

1. Simultaneous 10 Gbps data and clock transmission for smart power grid application utilizing the optical fibre and VCSEL technology.

Author

Aradi, H. E., Rotich Kipnoo, E. K., Masinde, F. W., Waswa, D. W., Jena, J., and Gibbon, T. B.

Subjects
*SMART power grids, *ELECTRIC power distribution grids, *LIGHT sources, *POWER transmission, *ERROR rates
Abstract

The study seeks to design a communication system for a power grid, that will ensure real-time and low-latency communication and automation between the utility and the end users. The performance characterization of the VCSEL in G.655 non-zero dispersion shifted fibre transmitting at 1550 nm is experimentally and theoretically analysed. The experiment reported the various evaluations of BER and eye diagrams using a VCSEL and a DFB laser as light sources. There was the successful achievement of 10 Gbps in 25 and 50 km for VCSEL and DFB respectively. In simultaneous data and clock transmission, 0.4 GHz and 10 Gbps over 25 km was successfully achieved using a VCSEL. The study is significant in the establishment of a pervasive communication system as the backbone of smart power grid design technology. [ABSTRACT FROM AUTHOR]

Published
2023
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2. Timing Operations

Author

Ünsalan, Cem, Gürhan, Hüseyin Deniz, Yücel, Mehmet Erkin, Ünsalan, Cem, Gürhan, Hüseyin Deniz, and Yücel, Mehmet Erkin

Published
2022
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5. Clock signal distribution with second order nodes: Design hints.

Author

Piqueira, José Roberto C. and de Godoi, Antonio Carlos B.

Subjects
DIGITAL communications, PHASE-locked loops, SYSTEMS design, DIGITAL technology, TELECOMMUNICATION
Abstract

Despite being in use since the 1960's, clock distribution networks continue to be important, mainly since the digitalization of numerous electronic tasks, which demands precise time measures for synchronizing internal and external processes in computational and instrumentation applications. Designing clock distribution networks requires determination/estimation of the appropriate topologies and parameters that guarantee the mutual synchronization of the coupled oscillators. This problem has been largely studied in the telecommunications context, with digital hierarchies succeeding at providing precise multiplexing and switching, integrating services, and in the process, giving rise to a new era of communication. From a mathematical viewpoint, this work considers linear coupling factors, with the study of nonlinear effects still open. As the nodes of time distribution networks are phase-locked loops, considering nonlinearities is helpful for the design and operation of such systems. Herein, an overview of possible solutions concerning topologies and parameters is presented, allowing performance hints regarding network architectures and parameters to help designers. The main contribution is to put together and compare each solution while taking nonlinearities into account and to associate the application to be supported with the best clock distribution solution, thus providing simple rules of thumb for system design. • Acceptable one-way clock distribution networks are chain or star. • Acceptable two-way clock distribution networks are chain or double-loop. • In well controlled environments, one way topologies are better solutions. • In noisy environments, two way topologies are better solutions. [ABSTRACT FROM AUTHOR]

Published
2021
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7. Sequential Circuits

Author

Deschamps, Jean-Pierre, Valderrama, Elena, Terés, Lluis, Deschamps, Jean-Pierre, Valderrama, Elena, and Terés, Lluís

Published
2017
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10. 便携式机箱内部 PCB 间微带线的耦合特性分析.

Author

吴其霖, 谭康伯, and 路宏敏

Abstract

A modeling and simulation analysis method based on model simplification is proposed to solve the problem of electromagnetic coupling interference in the microstrip line of PCB, which is connected to each module in the small interior of the portable chassis and is responsible for the function of information energy transmission and exchange. In this paper, the chassis model is modeled and simplified according to the micro - winding theory. Combined with the electromagnetic model modeling of the PCB inside the chassis and the microstrip line on it, and the adding of corresponding clock signal excitation and load on the microstrip line, the simulation analysis of the coupling characteristics of the microstrip line without PCB is realized. The results show that when the relative spatial position of the interference PCB is perpendicular or parallel, the coupling voltage peaks of the microstrip line are 1. 3 mv and 0. 5 mv, respectively. The overall change trend is related to the rising and falling edge of clock signal, and the coupling voltage on the vertical and parallel PCB is positively and negatively correlated, respectively. [ABSTRACT FROM AUTHOR]

Published
2021
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11. 9 ps TDC based on multiple sampling in 0.18 μm complementary metal–oxide–semiconductor.

Author

Jin, Shuowei, Chai, Jiaxin, Li, Jingjiao, and Yan, Aiyun

Abstract

A high‐precision measurement method, based on multiple sampling, is proposed for the time interval of two signals in this study. A time interval measurement circuit integrated into the time‐to‐digital converter (TDC), is designed based on this high‐precision measurement method. In the TDC, the authors use two identical delay lines as the holding module to ensure the two signals with a constant time interval. The TDC samples the two signals multiple times by a clock signal, whose period is shorter than that of the delay line. Consequently, the problem of limited resolution caused by a mismatch between delay lines in the delay‐line structure can be avoided, and the precision of the output can be improved. The proposed TDC is designed and simulated in Semiconductor Manufacturing International Corporation (SMIC) 0.18 μm complementary metal–oxide–semiconductor process. Simulation results show that the differential non‐linearity and the integral non‐linearity are always less than one least significant bits. The proposed TDC achieves input dynamic range of 0–32.13 ns and time resolution of 9 ps. [ABSTRACT FROM AUTHOR]

Published
2020
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13. Quantum Dot Cellular Automata (QDCA)

Author

Khanna, Vinod Kumar, Avouris, Phaedon, Series editor, Bhushan, Bharat, Series editor, Bimberg, Dieter, Series editor, von Klitzing, Klaus, Series editor, Ning, Cun-Zheng, Series editor, Wiesendanger, Roland, Series editor, and Khanna, Vinod Kumar

Published
2016
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17. Conclusions

Author

Wiśniewski, Remigiusz, Grimble, Michael J., Series editor, Johnson, Michael A., Series editor, and Wiśniewski, Remigiusz

Published
2017
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18. QuCTS—Single-Flux Quantum Clock Tree Synthesis

Author

Eby G. Friedman, Tahereh Jabbari, and Rassul Bairamkulov

Subjects
Computer science, Clock signal, Pipeline (computing), Overhead (engineering), Clock skew, Computer Graphics and Computer-Aided Design, CMOS, Logic gate, Rapid single flux quantum, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, Electrical and Electronic Engineering, Software, Hardware_LOGICDESIGN, Electronic circuit
Abstract

Superconductive Rapid Single Flux Quantum (RSFQ) is an emerging cryogenic technology promising a significant boost in performance and ultra-low power consumption. The operating frequency achieved by RSFQ digital integrated circuits is several orders of magnitude greater than traditional CMOS circuits. The fundamental difference of RSFQ circuits, however, renders traditional clocking techniques appropriate for CMOS unsuitable for RSFQ technology. Most RSFQ logic gates, such as AND and OR, are sequential in nature. The number of pipeline stages is therefore significantly greater in RSFQ as compared to CMOS, complicating the clock distribution network design process. This issue is further exacerbated with the need for splitters to achieve a fanout greater than one and the need for transmission lines rather than ordinary metallic wires as in CMOS. In this work, QuCTS — single flux Quantum Clock Tree Synthesis — is presented. QuCTS utilizes a two stage framework for synthesizing clock networks. In the clock skew scheduling stage, the clock signal arrival time of each gate is chosen to maximize the robustness of the circuit to timing variations. In the clock tree synthesis stage, the layout of the clock distribution network is generated based on a novel delay equilibration technique. QuCTS is the first clock tree synthesis tool for RSFQ circuits utilizing useful clock skew. The synthesized network satisfies the clock arrival time requirements while minimizing the associated overhead, such as the interconnect length and number of delay elements. The tool is validated on a set of benchmark circuits. In a prototypical case study, a clock tree is generated for the AMD2901 with 1,049 clock sinks in 53 minutes while satisfying the clock arrival time.

Published
2022

19. A Programmable Multiple Frequencies Clock Generator With Process and Temperature Compensation Circuit for System on Chip Design

Author

Lu-Chun Yeh, Kuo-Ning Chang, and Wei-Bin Yang

Subjects
Computer Networks and Communications, Clock signal, business.industry, Computer science, Circuit design, Electrical engineering, Hardware_PERFORMANCEANDRELIABILITY, Ring oscillator, Chip, Computer Science Applications, Compensation (engineering), Voltage-controlled oscillator, Control and Systems Engineering, Hardware_INTEGRATEDCIRCUITS, Clock generator, Electrical and Electronic Engineering, business, Information Systems, Jitter
Abstract

This article presents a programmable multiple frequencies clock generator with a process and temperature compensation circuit design. The proposed clock generator can achieve a stable and wide frequency range output for a single input frequency by using digital control codes as well as process and temperature compensation mechanisms. In our approach, the first step is to adjust the duty-cycle of the input clock by using a digitally controlled pulsewidth modulator (DCPWM) to generate an output clock signal with a duty-cycle of 20% to 80%. Second, the various duty-cycle clock outputs of the DCPWM are integrated by the duty-cycle-to-voltage converter to generate analog voltage signals to control the succeeding voltage-controlled ring oscillator (VCO). Through the use of various control voltages, different VCO output frequencies are generated. Finally, by using the process and temperature compensation circuit, the proposed clock generator can provide a stable and wide frequency range. The proposed chip is fabricated in a 180-nm CMOS process and has an output frequency range of 35–138 MHz at a supply voltage of 0.9 V. At 120 MHz, the power dissipation and rms jitter are 224.3 μW and 7.84 ps, respectively. The active area of the chip is 0.62 mm × 0.76 mm.

Published
2022

21. Designing Hardware for FPGAs

Author

Muthuswamy, Bharathwaj, Banerjee, Santo, Zelinka, Ivan, Series editor, Adamatzky, Andrew, Series editor, Chen, Guanrong, Series editor, Muthuswamy, Bharathwaj, and Banerjee, Santo

Published
2015
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23. Telemetry System for Cochlear Implant Using ASK Modulation and FPGA

Author

Martínez–Rams, Ernesto A., Garcerán–Hernández, Vicente, Sánchez, Duarte Juan, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Ferrández Vicente, José Manuel, editor, Álvarez-Sánchez, José Ramón, editor, de la Paz López, Félix, editor, Toledo-Moreo, Fco. Javier, editor, and Adeli, Hojjat, editor

Published
2015
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24. Evidence of a Larger EM-Induced Fault Model

Author

Ordas, S., Guillaume-Sage, L., Tobich, K., Dutertre, J.-M., Maurine, P., Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Joye, Marc, editor, and Moradi, Amir, editor

Published
2015
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25. Interconnection

Author

Ezz-Eldin, Rabab, El-Moursy, Magdy Ali, Hamed, Hesham F. A., Ezz-Eldin, Rabab, El-Moursy, Magdy Ali, and Hamed, Hesham F. A.

Published
2015
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29. On-Chip Debug Architecture

Author

Vermeulen, Bart, Goossens, Kees, Dutt, Nikil D., Series editor, Martin, Grant, Series editor, Marwedel, Peter, Series editor, Vermeulen, Bart, and Goossens, Kees

Published
2014
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31. Acoustic Detection and Ranging Using Solvable Chaos

Author

Corron, Ned J., Stahl, Mark T., Blakely, Jonathan N., Pethel, Shawn D., Abarbanel, Henry, Series editor, Braha, Dan, Series editor, Érdi, Péter, Series editor, Friston, Karl, Series editor, Haken, Hermann, Series editor, Jirsa, Viktor, Series editor, Kacprzyk, Janusz, Series editor, Kaneko, Kunihiko, Series editor, Kelso, Scott, Series editor, Kirkilionis, Markus, Series editor, Kurths, Jürgen, Series editor, Nowak, Andrzej, Series editor, Reichl, Linda, Series editor, Schuster, Peter, Series editor, Schweitzer, Frank, Series editor, Sornette, Didier, Series editor, Thurner, Stefan, Series editor, In, Visarath, editor, Palacios, Antonio, editor, and Longhini, Patrick, editor

Published
2014
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32. NanoMagnet Logic: An Architectural Level Overview

Author

Vacca, Marco, Graziano, Mariagrazia, Wang, Juanchi, Cairo, Fabrizio, Causapruno, Giovanni, Urgese, Gianvito, Biroli, Andrea, Zamboni, Maurizio, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Kobsa, Alfred, Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Anderson, Neal G., editor, and Bhanja, Sanjukta, editor

Published
2014
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33. Understanding a Bisferrocene Molecular QCA Wire

Author

Pulimeno, Azzurra, Graziano, Mariagrazia, Antidormi, Aleandro, Wang, Ruiyu, Zahir, Ali, Piccinini, Gianluca, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Kobsa, Alfred, Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Anderson, Neal G., editor, and Bhanja, Sanjukta, editor

Published
2014
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34. ToPoliNano: NanoMagnet Logic Circuits Design and Simulation

Author

Vacca, Marco, Frache, Stefano, Graziano, Mariagrazia, Riente, Fabrizio, Turvani, Giovanna, Roch, Massimo Ruo, Zamboni, Maurizio, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Kobsa, Alfred, Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Anderson, Neal G., editor, and Bhanja, Sanjukta, editor

Published
2014
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35. Emulating Cellular Automata in Chemical Reaction-Diffusion Networks

Author

Scalise, Dominic, Schulman, Rebecca, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Kobsa, Alfred, Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Murata, Satoshi, editor, and Kobayashi, Satoshi, editor

Published
2014
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40. Design of True Random Number Generator Based on Multi-Stage Feedback Ring Oscillator

Author

Huaguo Liang, Jianguo Cui, Zhengfeng Huang, Lu Yingchun, Maoxiang Yi, Di Cao, Tianming Ni, Haochen Qi, Wang Xinyu, and Liang Yao

Subjects
Phase-locked loop, Random number generation, Clock signal, Computer science, Electronic engineering, Ring oscillator, Hardware_ARITHMETICANDLOGICSTRUCTURES, Electrical and Electronic Engineering, Field-programmable gate array, Throughput (business), Randomness, Jitter
Abstract

True random number generators (TRNGs) play an important role in encryption systems. In this paper, a novel method of generating true random numbers on a field-programmable gate array (FPGA) is proposed based on the random jitter of a multi-stage feedback ring oscillator(MSFRO) as the entropy source. Based on the traditional ring oscillator, a multi-stage feedback structure is added to enlarge the range of clock jitter, and improve the frequency of clock sampling and the randomness of the entropy source. Different from the traditional clock sampling structure, we use the clock jitter signal generated by the MSFRO to sample the clock signal generated by the phase-locked loop (PLL) of the FPGA. The obtained output value is operated by XOR to reduce the deviation of the output value and improve its randomness. The TRNG is implemented in Xilinx Virtex-6 FPGA, which has low hardware resource consumption and high throughput. The entropy source classification, hardware resources and throughput are compared with those of existing TRNGs. The results showed that the proposed TRNG only consumed 24 LUTs and 2 DFFs. Compared with other TRNGs, this design has very low hardware resource consumption and its throughput is up to 290Mbps. The random bit sequence generated by this TRNG passes the NIST SP800-22 test and the NIST SP800-90B test.

Published
2022

41. Power-Oriented Monitoring of Clock Signals in FPGA Systems for Critical Application

Author

Oleksandr Drozd, Grzegorz Nowakowski, Anatoliy Sachenko, Viktor Antoniuk, Volodymyr Kochan, and Myroslav Drozd

Subjects
safety-related system, component, FPGA-designing, logical and power-oriented checkability, hidden faults, clock signal, Chemical technology, TP1-1185
Abstract

This paper presents a power-oriented monitoring of clock signals that is designed to avoid synchronization failure in computer systems such as FPGAs. The proposed design reduces power consumption and increases the power-oriented checkability in FPGA systems. These advantages are due to improvements in the evaluation and measurement of corresponding energy parameters. Energy parameter orientation has proved to be a good solution for detecting a synchronization failure that blocks logic monitoring circuits. Key advantages lay in the possibility to detect a synchronization failure hidden in safety-related systems by using traditional online testing that is based on logical checkability. Two main types of power-oriented monitoring are considered: detecting a synchronization failure based on the consumption and the dissipation of power, which uses temperature and current consumption sensors, respectively. The experiments are performed on real FPGA systems with the controlled synchronization disconnection and the use of the computer-aided design (CAD) utility to estimate the decreasing values of the energy parameters. The results demonstrate the limited checkability of FPGA systems when using the thermal monitoring of clock signals and success in monitoring by the consumption current.

Published
2021
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42. Memoryless Logic Circuit Design Based on the Quantum Phase Slip Junctions for Superconducting Digital Applications

Author

Satyabrata Jit, Azam Malekpoor, and Seyed Amir Hashemi

Subjects
Interconnection, Adder, Demultiplexer, OR gate, Computer science, Clock signal, business.industry, Electrical engineering, Hardware_PERFORMANCEANDRELIABILITY, Condensed Matter Physics, Multiplexer, Electronic, Optical and Magnetic Materials, Logic gate, Hardware_INTEGRATEDCIRCUITS, Hardware_ARITHMETICANDLOGICSTRUCTURES, Electrical and Electronic Engineering, business, Hardware_LOGICDESIGN, Electronic circuit
Abstract

In this article, the quantum phase slip junction (QPSJ) based full adder, multiplexer, and demultiplexer memoryless circuits for superconducting digital applications are designed for the first time. Generally, the memoryless circuits are implemented by interconnection of the basic gates (i.e., AND, OR, NOT). So in this article, the structures of the QPSJ-based AND and OR gates are also modified in order to reduce the complexity of their connections to the other gates by removing or changing the location of the clock pulse from their output branches. When a gate is connected to the next one, the elements of the second gate are loaded to the circuit of the first gate. The output current of the first gate will be affected due to this loading and no Cooper pair may be produced at its output and the next connected gate will not be switched. Therefore, the main tip in designing of these circuits is that each constituent gate must provide the necessary output current to drive the next connected gates, since each gate is driven by one Cooper pair. In this article, providing sufficient output current for each gate has been observed by 1) selecting proper critical voltages of the QPSJs and 2) by adding extra elements to or removing some elements from the connected gates in the proposed memoryless circuits.

Published
2021

43. Double Edge-Triggered Half-Static Clock-Gating D-Type Flip-Flop

Author

Chi-Wah Kok, Wing-Kong Ng, and Wing-Shan Tam

Subjects
Physics, TK7800-8360, Clock signal, Double edge, Clock gating, Topology (electrical circuits), Hardware_PERFORMANCEANDRELIABILITY, Topology, TK1-9971, Power (physics), law.invention, Reduction (complexity), CMOS, law, Hardware_INTEGRATEDCIRCUITS, Electrical engineering. Electronics. Nuclear engineering, Electronics, Hardware_ARITHMETICANDLOGICSTRUCTURES, Flip-flop, Hardware_LOGICDESIGN
Abstract

A double edge-triggered D-type flip flop includes a half-static clock gating circuit is presented in this paper. Two dynamic latches that each responses to the rising and falling edges of the gated clock are connected in parallel to a half-static latch, which captures the data signal in response to both rising and falling edges of the clock signal. This flip flop topology helps to improve the race tolerance, energy efficiency and circuit compactness. The flip flop is simulated with HSPICE using commercially 0.18 µm CMOS technology. The simulation results presented in this paper showed that it can achieve a 4 Gbits/sec data rate with 96% redundant power reduction when compared to other double edge-triggered D-type flip flop in literature.

Published
2021

45. DC-DC Conversion

Author

Marien, Hagen, Steyaert, Michiel, Heremans, Paul, Marien, Hagen, Steyaert, Michiel, and Heremans, Paul

Published
2013
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