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Digital single-flux quantum (SFQ) technology promises to meet the demands of ultralow-power and high-speed computing needed for future exascale supercomputing systems. However, high degrees of variability makes ultrahigh-speed low-skew clock distribution of large-scale SFQ circuits challenging. This article proposes to mitigate this problem by supporting multiple independent SFQ clock domains with the design of reliable clock domain crossing (CDC) circuits. We first show that previously proposed CDC first-in-first-out buffers (FIFOs) are vulnerable to synchronization errors, motivating the need for more robust CDC FIFOs. Inspired by complementary metal-oxide-semiconductor (CMOS) multi-flip-flop FIFO synchronizers, we then present a metastability-resilient SFQ FIFO synchronizer that, simulations show, delivers over a 1000 reduction in logical error rate at 30 GHz. We show that, for a 10-stage FIFO, the Josephson junction area of our proposed design is only 7.5% larger than the nonresilient counterpart. Finally, we propose detailed design guidelines that define the minimal depth of our proposed synchronizers subject to both throughput and burstiness constraints.

In the practical ASIC and SOC designs the multiple clocks are used and the designs are called as multiple clock domain designs. These kinds of designs need to be described using the efficient design architectures and Verilog RTL. This chapter focuses in the key design techniques which are used to describe the multiple clock domain designs while passing data from one of the clock domain to other. The chapter key highlights are the detail description for the synchronizers, data path, and control path synchronization logic using the efficient Verilog RTL. This chapter also discusses on the key design challenges in the multiple clock domain designs and even this chapter focuses on the design guidelines to describe the efficient clock domain designs.

A novel approach of clock domain crossing solution is presented. For high-frequency conditions traditional approach calls for multiple D-flops for single bit synchronization. The higher the frequency the higher the number of flops. In high-frequency solutions, such an approach can consume much-needed space and limit the useful area for additional logic. Hence a new mixed-signal circuit is introduced which can be used in high-frequency applications to reduce the overall area of synchronizer logic used for single-bit synchronization. Comparison has been done for traditional multi-flop synchronization and proposed design with analog comparators. Unlike traditional design, the proposed circuit has no additional delays in form of additional clock cycles. For the usual use case of a two-stage synchronizer, the proposed design has 20% more area, but in high-frequency applications, where three or more synchronization stages are used, at least 30% are reduction was achieved (the higher the stage number, the more reduction percentage). The simulation was performed with SAED 32/28 nm technology.

Verification is an important part of the Electronic Design Automation (EDA) design flow which currently takes a considerable amount of time. During the synthesis process, Different optimizations are done to the Register-Transfer-Level (RTL) code to optimize the power, area, and speed of the circuit. These optimizations result in changes in the names of signals at the gate level. Automatic signal mapping can improve the verification process and can be used to guide functional verification activities between the two presentations using (Clock domain crossing (CDC) analysis in RTL, Gate Level CDC) as well as Formal Sequential Equivalence Checking. Machine Learning has applications everywhere in our lives, and EDA is not an exception. Machine Learning can help EDA tools optimize their results by learning from their previous choices which would improve their results. Machine Learning can help in decreasing the amount of time used in the verification process and increase productivity. In this paper, we discuss the methods used in the signal correlation, propose a modification to one of them as well as present a new technique using Machine Learning to solve the problem of signal correlation between the RTL and the gate level.

Communication between different IP cores in MPSoCs and HMPs often results in clock domain crossing. Asynchronous network on chip (NoC) support communication in such heterogeneous set-ups. While there are a large number of tools to model NoCs for synchronous systems, there is very limited tool support to model communication for multi-clock domain NoCs and analyse them. In this article, we propose the P luggable A synchronous NE twork on Chip (PANE) simulator, which allows system-level simulation of asynchronous network on chip (NoC). PANE allows design space exploration of synchronous, asynchronous, and mixed synchronous-asynchronous(heterogeneous) NoC for various system-level NoC parameters such as packet latencies, throughput, network saturation point and power analysis. PANE supports a large range of NoC configurations—routing algorithms, topologies, network sizes, and so on—for both synthetic and real traffic patterns. We demonstrate the application of PANE by using synchronous routers, asynchronous routers, and a mix of asynchronous and synchronous routers. One of the key advantages of PANE is that it allows a seamless transition from synchronous to asynchronous NoC simulators while keeping pace with the developments in synchronous NoC tools as they can be integrated with PANE.

As the technology nodes are getting smaller and smaller the design of a SoC is becoming more complex day by day. Modern day SoCs are a collection of individual intellectual properties [IP]. Each IP has its own clocking regime and each clock belongs to the separate clock domains. This leads to the challenge in design and verification of SoCs. Designing of the SoCs involves proper synchronization schemes to be employed to synchronize signals crossing clock domains. The functional verification of SoCs is becoming more and more difficult due to the data transferred between individual IP modules. When data transfers between two IPs the data crosses clock domains leading to clock domain crossing [CDC]. For a SoC to be free of all CDC errors, verification is paramount along with meeting the timing requirements. The present work focuses on reduction of waivers and improving the QoR and the coverage of the design. This work also focuses on the verification of functionality of the synchronizers by simulation and assertion-based verification. Then finally to close the gap from verification to sign-off, the assertions are converted to equivalent timing checks and are validated through timing analysis. The results show that the methodology shows a reduction of waivers by 45% and improved the design coverage to 93%.

According to Moore's Law, number of transistors on chip doubles in every next two years, So the complexity of the circuit increases. So it needs to be careful in designing and verification. Register Transfer Level (RTL) designing and its verification is also most important part of circuit design. The intent behind verification is to check that design meets all system specification and requirements or not. It is important to verify RTL before simulation and synthesis the design because It save clock cycle and time of simulation. This paper is focused on the RTL verification tool, Such as HAL linting and Spyglass RTL signoff tool. This type of RTL verification is used to find bugs and error in design before synthesis. It is easy to debug RTL design and pinpoint the problem and their solution. It is important to identify design issues as early as possible before synthesis RTL design.

In this paper, an attempt has been made to propose a methodology for detecting glitch on clock tree, reset trees, and clock domain crossing (CDC) paths. These glitches, if not verified appropriately, will cause chip re-spins when detected late in the design cycle. Modern designs contain multiple IPs from different sources, and when they are integrated, glitch prone logic can be introduced unintentionally. At the same time, CDC paths with multiplexers or combinational logic are prone to glitch defects being introduced by synthesis. These glitches may be captured by a register when crossing clock domains, causing a functional failure. So, it becomes essential to catch glitch issues in the design in an early phase of the design cycle.

The increasing complexity and modularity of contemporary systems, paired with increasing parameter variabilities, makes the availability of flexible and robust, yet efficient, module-level interconnect instrumental. In this context Globally Asynchronous Locally Synchronous (GALS) systems offer a viable alternative to classical strictly synchronous interconnect. However, with this concept a need for reliable interfaces between different clock and timing domains arises. In this paper we propose a novel approach for timing domain crossing interfaces which are able to safely transfer (read) tokens (i.e., zero-bit messages) from a synchronous into an asynchronous timing domain and vice versa. At its core the new approach uses a Muller pipeline where read tokens are synchronously written to and read from. Doing this in a way that does not lose any tokens, requires the synchronous timing domain to have exact state information about the fill-level of the Muller pipeline (i.e., is it safe to perform a write or read operation). We thoroughly analyze how this state information can be obtained and propose a simple pipeline sampling model. Furthermore we discuss what timing constraints these concepts rely on and how to deal with metastability that inevitably appears at such interfaces. One possible use of the proposed structures is the control path of synchronous/asynchronous or bisynchronous FIFOs, which we use to illustrate the principle and show the practical feasibility.

This paper studies the impact of clock mismatches and quantization on networked control systems. We consider a scenario where the plant's state is measured by a sensor that communicates with the controller through a network. Variable communication delays and clock jitter do not permit a perfect synchronization between the clocks of the sensor and controller. We investigate limitations on the clock offset tolerable for stabilization of the feedback system. For a process with a scalar-valued state, we show that there exists a tight bound on the offset above which the closed-loop system cannot be stabilized with any causal controllers. For higher dimensional plants, if the plant has two distinct poles, then the effect of clock mismatches can be canceled with a finite number of measurements, and hence there is no fundamental limitation. We also consider the case where the measurements are subject to quantization in addition to clock mismatches. For first-order plants, we present necessary conditions and sufficient conditions for stabilizability, which show that a larger clock offset requires a finer quantization.

A new all-digital multiplying delay-locked loop (MDLL) is presented that can provide programmable fractional-ratio frequency synthesis of a de-skewed clock. The proposed fractional-ratio MDLL (FMDLL) employs a new select logic for controlling three operation modes and utilizes a new phase-detecting structure to achieve inherent cancellation of the internal phase offset. The proposed digital FMDLL is implemented in a 65-nm 1-V CMOS process and occupies an area of 0.019 mm 2 with programmable frequency ratios of N = 1, 4, 5, 8, 10, and M = 1, 2, 3. It operates over a frequency range of 0.7-2.0 GHz and achieves an effective peak-to-peak jitter of 10 ps at 2 GHz when N/M = 8/2. It achieves a locking time of only 40 clock cycles and dissipates 3.3 mW at 1 GHz when N/M = 1/1. The FMDLL employs a new harmonic lock detector to eliminate the harmonic lock problem and achieve dynamic switching of the clock frequencies and division ratios.

In this research, we propose the Clock Synchronization by Least Common Multiple (CSLCM) method to remove the clock offset and clock skew among the sensor nodes. The proposed CSLCM enables the nodes to reach a network synchronization time by calculating the least common multiple of their Clock Time Period (CTP). The network is organized into clusters and every node reaches the network synchronization time using its own CTP. Simulation results show that, the CSLCM algorithm is more efficient compared to the Average Time Synchronization with Pairwise messages (ATSP) in terms of accuracy, communication overhead, and computation overhead.

In this paper, a method has been proposed by which one can reduce the clock jitter and achieve almost flat frequency clock output from the phase-locked loop (PLL), independent of the power supply voltage fluctuation. These voltage fluctuations occur when a given chip comes out from the sleep mode to the active mode. This causes the chip to draw a hasty current, which in turn produces LdI/dt noise. That causes the voltage to drop and also to oscillate at the power delivery network’s resonance frequency. This power supply noise causes clock jitter. The voltage-controlled oscillator of the proposed PLL is designed at 45-nm technology such that when there is supply voltage variation, it is automatically corrected by a feedback methodology having only 11-ps response time delay, compared to 588-ps clock period. Simulation result shows that, for the proposed new PLL design, the number of places where the clock periods are altered due to this power supply voltage fluctuation is reduced. The performance of the proposed PLL design in terms of reduction of clock jitter, caused by the variation of power supply voltage and the flatness of the frequency versus power supply voltages, is tested by feeding the clock to a circuit (c17 of ISCAS’85) for the conventional methodology and also for our new methodology. It has been shown that, using the proposed method, the clock jitter caused by the power supply noise can be reduced by about 50% compared to the conventional design methodology.

A space-filling clock tree is presented, which takes an advantage of LC resonant clocking, to obtain a uniform phase and amplitude multiply-by-3 clock from a unique Sierpinski-coupled ring oscillator (SCRO) array. The three-stage interleaved SCROs resemble the Sierpinski triangle, and are synchronized with a common frequency to all. The SCRO further provides an aligned output phase relationship to reduce skew. The triangle clock grid with a side length of 3.2 mm is filled by a space-filling clock tree. The 3-D stacked transformers at the tree endpoints extract the third harmonic of the SCRO array oscillation and scale the voltage amplitude of the extracted clock. The transformers also perform a built-in bandpass filtering function to remove injected noise. An experimental prototype integrated in a 90-nm CMOS operates at 2.85–4.3 GHz and consumes 19.2–49 mW under 0.7–1 V supply voltages. With 300-mV added supply noise, jitter was measured as 3.4 ps (rms) and 17.7 ps (pp). The measured results reveal substantial improvements in both power and jitter from this approach.

In the paradigm of stochastic computing, arithmetic functions are computed on randomized bit streams. The method naturally and effectively tolerates very high clock skew. Exploiting this advantage, this paper introduces polysynchronous clocking, a design strategy in which clock domains are split at a very fine level. Each domain is synchronized by an inexpensive local clock. Alternatively, the skew requirements for a global clock distribution network can be relaxed. This allows for a higher working frequency and so lower latency. The benefits of both approaches are quantified. Polysynchronous clocking results in significant latency, area, and energy savings for wide variety of applications.

This paper proposes an integrated shift register circuit for an in-cell touch panel that is robust over clock noises. It is composed of 10 thin film transistors and 1 capacitor, and the time division driving method is adopted to prevent the negative effect of display signals on the touch sensing. Two pre-charging nodes are employed for reducing the uniformity degradation of gate pulses over time. In particular, the proposed circuit connects a drain of the first pre-charging node's pull-up thin film transistor (TFT) to the positive supply voltage instead of clock signals. This facilitates to lower coupling noises as well as to clock power consumption. The simulation program with an integrated circuit emphasis is conducted for the proposed circuit with low temperature poly-silicon TFTs. The positive threshold voltage that shifts up to 12 V at the first pre-charging pull-up TFT can be compensated for without the uniformity degradation of gate pulses. For a 60-Hz full-HD display with a 120-Hz reporting rate of touches, the clock power consumption of the proposed gate driver circuit is estimated as 7.13 mW with 160 stages of shift registers. In addition, the noise level at the first pre-charging node is lowered to −28.95 dB compared with 2.37 dB of the previous circuit.

The aim of this letter is to improve the performance of clock synchronization in EtherCAT networks. Although EtherCAT synchronizes the slave clocks to the reference clock using a distributed clock synchronization mechanism, a synchronization error still exists between them. We propose a method to estimate and significantly reduce this error. In addition, we implement the method within the existing synchronization mechanism without adding an excessive computational load. The experimental results for synchronization performance verify that the proposed method improves the accuracy of clock synchronization in EtherCAT networks.

This brief describes the design and implementation of a 250-Mb/s to 6-Gb/s single-loop referenceless clock and data recovery circuit. The clock frequency multiplier and the referenceless frequency acquisition circuit are used to cover a wide-range data rate. The clock frequency multiplier is proposed to generate the 6-GHz clock with low jitter. In addition, the voltage-controlled oscillator operates at 1/5-rate frequency of the sampling clock, which has a merit of low power consumption. The proposed circuit achieves 9.56-ps rms jitter, consumes 13.2 mW at 6 Gb/s, and occupies 0.0944 mm2 in a 65-nm CMOS technology.

Design techniques to improve energy efficiency of serial link transceivers are presented. Power consumption is reduced by using: 1) low-power clock generation, recovery, and distribution schemes; 2) charge-based circuits to implement analog front-end and samplers/flip-flops; and 3) a partially segmented voltage-mode (VM) output driver. An $LC$ -oscillator based digital phase-locked loop (PLL) is used to generate a low jitter clock that is shared between the transmitter (Tx) and receiver (Rx). The clock recovery unit uses a local ring-oscillator based PLL to reduce the number of phase interpolators and the amount of high-frequency clock distribution. Charge-based samplers that were shown to operate with limited return-to-zero voltage swings and consume only dynamic power are modified to provide non-return-to-zero outputs and used extensively in the deserializer and Rx front-end circuits. A partially segmented VM output driver with embedded 2-tap de-emphasis is proposed to reduce power consumption of pre-drivers. Fabricated in a 65 nm CMOS process, the 14 Gb/s transceiver prototype employs aforementioned techniques and achieves an energy efficiency of 2.8 mW/Gb/s. The Tx achieves a phase margin of 0.36 UI (BER = 10−12) at the end of an 11 dB loss channel with an energy efficiency of 0.89 mW/Gb/s. The Rx recovers clock with 1.8 psrms long term absolute jitter at BER $LC$ -oscillator based digital PLL achieves an integrated jitter of 0.605 psrms with an energy efficiency of 0.5 mW/GHz at 7 GHz output frequency.

We propose efficient algorithms to construct a low-power clock tree for through-silicon-via (TSV)-based 3D-ICs. We use shutdown gates to save clock trees’ dynamic power, which selectively turn off certain clock tree branches to avoid unnecessary clock activities when the modules in these tree branches are inactive. While this clock gating technique has been extensively studied in 2D circuits, its application in 3D-ICs is unclear. In 3D-ICs, a shutdown gate is connected to a control signal unit through control TSVs, which may cause placement conflicts with existing clock TSVs in the layout due to TSV’s large physical dimension. We develop a two-phase clock tree synthesis design flow for 3D-ICs: (1) 3D abstract clock tree generation based on K-means clustering and (2) clock tree embedding with simultaneous shutdown gates’ insertion based on simulated annealing (SA) and a force-directed TSV placer. Experimental results indicate that (1) the K-means clustering heuristic significantly reduces the clock power by clustering modules with similar switching behavior and close proximity, and (2) the SA algorithm effectively inserts the shutdown gates to a 3D clock tree, while considering control TSV’s placement. Compared with previous 3D clock tree synthesis techniques, our K-means clustering-based approach achieves larger reduction in clock tree power consumption while ensuring zero clock skew.

Time synchronization plays an important role in the spacecraft formation flight and constellation autonomous navigation, etc. For the application of clock synchronization in a network system, it is not always true that all the observed nodes in the network are interconnected, therefore, it is difficult to achieve the high-precision time synchronization of a network system in the condition that a certain node can only obtain the measurement information of clock from a single neighboring node, but cannot obtain it from other nodes. Aiming at this problem, a novel method of high-precision time synchronization in a network system is proposed. In this paper, each clock is regarded as a node in the network system, and based on the definition of different topological structures of a distributed system, the three control algorithms of time synchronization under the following three cases are designed: without a master clock (reference clock), with a master clock (reference clock), and with a fixed communication delay in the network system. And the validity of the designed clock synchronization protocol is proved by both stability analysis and numerical simulation.

A dual-lane DC-to-12.5 Gb/s all-rate clock and data recovery (CDR) IC with a single LC voltage-controlled oscillator is fabricated in a 90 nm CMOS. An all-rate clock divider with an asynchronous phase calibration scheme is employed to generate all-rate clock signals without a phase mismatch or duty cycle distortion. The IC features an automatic loop gain control scheme that adjusts the bandwidth of a CDR in the background for optimal bit error rate (BER) performance by monitoring the phase difference between the incoming data and the recovered clock signal. The proposed CDR consumes 244 mW at 12.5 Gb/s under dual-lane operation with an input sensitivity of 12 mVpp,diff. The CDR supports referenceless allrate operation with a BER

In a high-performance VLSI design, the clock network consumes a significant amount of power. While most existing methodologies use voltage-mode (VM) signaling, these clock distributions lose a tremendous amount of dynamic power to charge/discharge the large global clock capacitance. New circuit approaches for current-mode (CM) clocking save significant clock power, but have been limited to only symmetric networks, while most application specific integrated circuits have asymmetric clock distributions. In this paper, we propose the first CM clock synthesis (CMCS) methodology to reduce the overall clock network power with low skew. The method can integrate with traditional clock routing followed by transmitter and receiver sizing. We validate the proposed methodology using ISPD 2009 and 2010 industrial benchmarks using an extracted SPICE model distributed in 1.4–275.6-mm2 area and consists of 81–2249 sinks. This methodology saves 39%–84% average power with similar skew on the benchmarks using 45-nm CMOS technology simulation of clock frequencies range from 1–3 GHz. In addition, the CMCS methodology takes $2.4-9.1\times $ less running time and consumes 20%–26% less transistor area compared with synthesized, buffered VM clock distributions.

Clock trees, which deliver the clock signal to every clock sink in the whole system, switch actively at high frequency, which makes them one of the most dominant sources of noise. While many clock polarity assignment (PA) techniques were proposed to mitigate the clock noise, no attention has been paid to the PA under useful skew constraints. In this work, we show that the clock PA problem under useful skew constraints is intractable and propose a comprehensive and scalable clique search based algorithm to solve the problem effectively. In addition, we demonstrate the applicability of our solution by extending it for PA under delay variation environment. Through experiments with ISPD'10 benchmark circuits, we show that our proposed clock PA algorithm is able to reduce the peak noise by 10.9% further over that of the conventional global skew bound constrained PA. Finally, we compare our PA technique against decoupling capacitor embedding technique which is a commonly used method for noise reduction. HighlightsWe propose a clock buffer polarity assignment algorithm under useful clock skew constraints that enables the consideration of individual setup and hold time constraints for the reduction of power and ground noise emitted by the clock trees.We prove that the polarity assignment under useful clock skews is intractable.A heuristic framework that is able to trade-off between the quality of solution and run-time is proposed.

Timestamp free clock synchronization in a master–slave network, i.e., synchronization where no timestamps are exchanged between the nodes, is considered. For highly accurate synchronization, a novel discrete-valued clock model is introduced. It is based on the observation that clocks are discrete counters in digital wireless radios. Considering this model, it is shown that the round-trip time (RTT) measurements follow specific pulse or step shaped functions. The estimated parameters of these RTT functions are used to determine the clock parameters (clock skew and phase) and the propagation delay. Numerical analysis illustrate that when RTT measurements are collected using discrete-valued clocks, the proposed estimation schemes outperform estimators derived from the continuous clock model, which is used in the state-of-the-art methods. Moreover, the presented scheme performs similar to recently presented discrete-valued clock approaches with more stringent hardware assumption. The correctness of the proposed models is validated through hardware experiments.

A simple circuit for duty-cycle correction is proposed in this paper. The configuration is flexible consisting of only three CMOS inverters in a feedback loop. It does not require any reference signal and, therefore, it can be used as a standalone circuit, while it can be applied on a single-ended clock path without breaking the clock line. Simulation results in a 65 nm CMOS technology and 1 V supply voltage give a duty-cycle error less than 1% for a duty-cycle input clock variation between 30 and 70% with a frequency range from 2.4 to 2.9 GHz.

With the application of internet in manufacturing, motion control system is tend to networking. Clock synchronization is a basic requirement to guarantee capability of coordination in networked motion control systems. In this paper, we propose a frequency-tracking clock servo (FTCS) to adjust the local clock to synchronize with the reference clock. The frequency of FTCS can rapidly lock onto the reference frequency and the offset can be fully compensated within a single synchronizing cycle. Simulations and experiments are performed to validate the feasibility and superiority of FTCS. Compared with the proportional-integral clock servo, FTCS can achieve the rapid synchronized speed and better precision with low frequency of sending synchronization messages.

The work solves a new problem of optimizing the boundary of buffered clock trees, which has not been addressed in the design automation as yet. Precisely, we want to show that the clock cells that directly drive flip-flops should not necessarily be buffers. By taking into account the internal structure of flip-flops, we can have a freedom of choosing either buffers or inverters for the cell implementation from library. This in fact leads to cancel out the two inverters, one in the driving buffer and another in each flip-flop, thereby reducing the power consumption on the clock tree, including flip-flops. We generalize this idea to look into the possibility of co-optimizing the driving buffers and flip-flops together to reduce the clock power at the boundary of clock trees, and propose an effective four-step synthesis algorithm of clock tree boundary for low power. By applying our proposed technique to benchmark circuits, it is observed that the clock power is able to be reduced by 4.45 % ~ 6.33 % further on average without timing violation.

This chapter explores one of the most critical aspects of multi-clocked designs, that being the clock domain crossing (CDC) logic. How do you use assertions to model CDC behavior and catch bugs thereof.

Many of today's chips comprise multiple clock domains and some even have multiple clock sources. This makes supervision of the correct operation of a clock increasingly important. Rather than promoting a specific approach for clock failure detection, this paper tries to provide a systematic overview of the available options. To this end, requirements and principles are identified and discussed first, and then related implementations are shown. These are partly revisiting existing solutions from the literature that are put into the context, and partly constituting novel solutions. The implementations are evaluated according to several criteria, like detection latency, implementation efforts, and, most notably, potential for metastability issues. The purpose of the paper is to give the designer a guideline, showing which techniques are available, along with a critical assessment that shall help in making the appropriate choice for a given application.

Digital single-flux quantum (SFQ) technology promises to meet the demands of ultra low power and high speed computing needed for future exascale supercomputing systems. The combination of ultra high clock frequencies, gate-level pipelines, and numerous sources of variability in SFQ circuits, however, make low-skew global clock distribution a challenge. This motivates the support of multiple independent clock domains and related clock domain crossing circuits that enable reliable communication across domains. Existing J-SIM simulation models indicate that setup violations can cause clock-to-Q increases of up to 100%. This paper first shows that naive SFQ clock domain crossing (CDC) first-in-first-out buffers (FIFOs) are vulnerable to these delay increases, motivating the need for more robust CDC FIFOs. Inspired by CMOS multi-flip-flop asynchronous FIFO synchronizers, we then propose a novel 1-bit metastability-resilient SFQ CDC FIFO that simulations show delivers over a 1000 reduction in logical error rate at 30 GHz. Moreover, for a 10-stage FIFO, the Josephson junction (JJ) area of our proposed design is only 7.5% larger than the non-resilient counterpart. Finally, we propose design guidelines that define the minimal FIFO depth subject to both throughput and burstiness constraints.

It is commonly held that because SOCs are extremely complex, the gap between the ability to design and to verify is beyond manageable proportions. Recent reality, though, has been more positive. The recent increase in SOC scale has been enabled by design-style advances, and the increase in SOC scale has been much more rapid than that of constituent IP. Consequently, verification complexity and SOC failure is now more correlated to SOC implementation schemes than IP functionality. In this milieu, SOC sign-off appears more manageable when broken into verification problems posed by the individual SOC implementation schemes, each scheme characterized by a narrow range of failure risks that can be modeled precisely. This tends to be a sweet spot for “static analysis”, which is a general term for methods that are based on algorithmically analyzing design attributes rather than testing a design by evaluating input stimuli through them. In fact, the dissection of SOC verification into the individual verification problems and the development of failure-specific static analysis methods for them has been the verification revolution of the past decade, without which the SOC revolution would have stalled.

The SpaceWire standard, used in aerospace embedded applications, was developed to connect devices that operate at high data rates, having as goals the traffic control and payload transmission. This standard enables flexibility on transmission rates, which brings some challenges related to clock domains. In an effort to fulfill the essential system requirements, such as reliability and versatility, synchronization techniques are introduced to avoid possible problems related to the clock domain crossing. The objective of this work is to present a technique applied to SpaceWire Receiver that enables its operation at many signaling rates.