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This paper presents the Thermal Resistance and Impedance Calculator (TRIC) tool devised for the automatic extraction of thermal metrics of package families of electronic components in both static and transient conditions. TRIC relies on a solution algorithm based on a novel projection-based approach, which&mdash, unlike previous techniques&mdash, allows (i) dealing with parametric detailed thermal models (pDTMs) of package families that exhibit generic non-Manhattan variations of geometries and meshes, and (ii) transforming such pDTMs into compact thermal models that can be solved in short times. Thermal models of several package families are available, and dies with multiple active areas can be handled. It is shown that transient thermal responses of chosen packages can be obtained in a CPU (central processing unit) time much shorter than that required by a widely used software relying on the finite-volume method without sacrificing accuracy.

This paper presents the thermal modeling of Ball Grid Array (BGA) package families using the Thermal Resistance and Impedance Calculator (TRIC) simulation tool. The intrinsic complexity and the great variability of the BGA families make it necessary the introduction of a calibrated thermal modeling strategy, exploiting some of the Authors experiences. In particular, the adoption of equivalent blocks to model the package structure drastically simplifies the geometry definition and the mesh issues to calculate the thermal data in a short amount of time, still guaranteeing the requested level of accuracy.

This paper presents the Thermal Resistance and Impedance Calculator (TRIC) simulation tool, extending the TRAC tool, for the automatic extraction of thermal metrics of package families of electronic components in both stationary and transient conditions. The determination of the thermal metrics is speeded up by an accelerated solution algorithm, based on a novel projection-based approach, which, unlike previous techniques, allows dealing with parametric detailed thermal models of package families exhibiting generic non-Manhattan variations of geometries and meshes.

Controlling warpage in backend manufacturing is a challenge that needs to be tackled in early design stage. Failure to do so may result in later manufacturability or reliability issues. This is of particular importance in BGA automotive packages where warpage could influence not only backend workability but also later thermal cycling reliability performance of the package mounted on board. Previous study has dealt separately with post Post Mold Curing (PMC) and post reflow processes. Experimental trials have been performed followed by material characterization tests and Finite Element Method (FEM) methodology development. This paper deals with a complete explanation of BGA warpage behavior in backend and provides a reliable guideline for new design bill of material selection with the intention to design for manufacturability and reliability at an early stage. In doing so design cycles can be significantly reduced as will be the need for exhaustive design of experiment.

A novel simulation tool, named Thermal Resistance Advanced Calculator, is presented Such a tool allows the straightforward definition of a parametric detailed thermal model of family of electronic packages with Manhattan geometry, in which anew thermal properties and/or geometrical details can vary in a chosen set. It then applies a novel parametric MOR-based approach for the automatic and fast extraction of a parametric compact thermal model of this family of electronic packages. Lastly, it automatically determines the JEDEC thermal metrics from this parametric compact thermal model for any choice of parameters in a negligible amount of time. The method is validated through the analysis of a family of exposed pad Quad Flat Packages.

The mechanical reliability of thin plastic packages during soldering reflow process on circuit board and thermal cycle becomes one of the most critical aspect in device mounting and operation. When a package is subjected to thermal loadings, deformation and deviation from an ideal uniform planar flatness usually result. Package warpage leads to thermo-mechanical issues at those sites of weak adhesion in the structure. The estimation of warpage is necessary for increasing package reliability. This paper deals with in-situ characterization of temperature-induced package warpage by adopting fringe pattern projection principle. The experimental analysis allows to evaluate real-time dynamic warpage at different target temperatures. In addition, numerical modeling is employed to identify the most critical material interface when a package is subjected to thermal loads. Simulation results are in good agreement with standard reliability trials on packages mounted on board.

Understanding and predicting warpage behavior during backend process is key to avoiding workability issues during manufacturing and later reliability issues during testing or during the device operational lifetime. To achieve this several challenges are encountered amongst which are the various temperature loadings that the material has to go through during processing. These temperature loadings can have different effects on warpage. This paper deals with understanding how different assembly processes can effect warpage with particular focus on the ball attach reflow assembly process.

When a plastic package is subjected to reflow, deformation and deviation from an ideal uniform planar flatness usually results. In the case of ball grid array (BGA) packages, warpage is caused by the thermal expansion mismatch between an organic substrate and other components constituting the package assembly. Substrate stack-up is mainly constituted of copper and core material. An accurate estimation of the coefficient of thermal expansion (CTE) of substrate materials becomes necessary for increasing package reliability during soldering reflow. This paper deals with in-situ characterization of in-plane deformation by adopting a methodology based on the digital image correlation (DIC) principle. First, the CTE measurement by DIC is validated by analysing copper laminates and comparing results with literature values. Then, the evaluation is performed for different components of the BGA substrate stack-up. The analysis allows to determine the CTE of these materials at various temperatures encountered during ball attach reflow process. Experimental results help to investigate the impact of the different components on the thermo-mechanical properties of organic substrates. In particular, it is found that copper has a major contribution during the heating-up stage of the soldering process, while core material behaviour becomes prominent during cooling-down.

Ceramic engineer and manufacturing executive, Philip E. Rogren will explain why molded array packages such as QFNs promise significant cost advantages compared to competitive packaging techniques. He will also describe why there are significant limitations for array packaging techniques based on lead frames. Audiences will learn about the feature of lead frame based packages that is responsible for virtually all of these limitations: Every package terminal and die paddle is a portion of the continuous metal structure that is the lead frame. Every terminal and die paddle is connected to, and held in proper position by, otherwise useless metal projections extending out of the package site to supporting portions of the lead frame. This planer, unitary structure presents limitations in the design of packages, limiting lead counts to around 70 leads and impacting performance because of increased lead to lead parasitic. The structure also adds process steps and cost to the assembly operation. In this presentation Rogren will describe a novel MAP substrate that features print formed, discrete terminal structures and die paddles arrayed on a sacrificial steel substrate. This structure eliminates the disadvantages of the interconnected lead frame based technology. In addition, this manufacturing process substantially reduces the pollution-causing process steps and it eliminates non-recyclable waste.

Optimization of 4 layer (4L) BGA thermal performance with best reliability and cost compromise is presented. Effects of design variables on thermal performance, reliability and cost are examined with both experiments and simulation. Long term thermal performance and solder joint reliability is also presented. It is found that removal of soldermask at DA are gives thermal improvement. With conventional DA, up to 20% soldermask opening can be used. It is demonstrated that by optimizing the die pad and solder mask pattern the thermal performance of a 4L BGA can be improved without degrade the reliability and addition cost.

Thermal behaviour of integrated circuit is increasingly important as the total power increases.