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The discipline of reverse engineering integrated circuits (ICs) is as old as the technology itself. It grew out of the need to analyze competitor’s products and detect possible IP infringements. In recent years, the growing hardware Trojan threat motivated a fresh research interest in the topic. The process of IC reverse engineering comprises two steps: netlist extraction and specification discovery. While the process of netlist extraction is rather well understood and established techniques exist throughout the industry, specification discovery still presents researchers with a plurality of open questions. It therefore remains of particular interest to the scientific community. In this paper, we present a survey of the state of the art in IC reverse engineering while focusing on the specification discovery phase. Furthermore, we list noteworthy existing works on methods and algorithms in the area and discuss open challenges as well as unanswered questions. Therefore, we observe that the state of research on algorithmic methods for specification discovery suffers from the lack of a uniform evaluation approach. We point out the urgent need to develop common research infrastructure, benchmarks, and evaluation metrics.

Printed electronics (PE) circuits have several advantages over silicon counterparts for the applications where mechanical flexibility, extremely low-cost, large area, and custom fabrication are required. The custom (personalized) fabrication is a key feature of this technology, enabling customization per application, even in small quantities due to low-cost printing compared with lithography. However, the personalized and on-demand fabrication, the non-standard circuit design, and the limited number of printing layers with larger geometries compared with traditional silicon chip manufacturing open doors for new and unique reverse engineering (RE) schemes for this technology. In this paper, we present a robust RE methodology based on supervised machine learning, starting from image acquisition all the way to netlist extraction. The results show that the proposed RE methodology can reverse engineer the PE circuits with very limited manual effort and is robust against non-standard circuit design, customized layouts, and high variations resulting from the inherent properties of PE manufacturing processes.

The ZX-calculus is a graphical language for reasoning about quantum computation using ZX-diagrams, a certain flexible generalisation of quantum circuits that can be used to represent linear maps from $m$ to $n$ qubits for any $m,n \geq 0$. Some applications for the ZX-calculus, such as quantum circuit optimisation and synthesis, rely on being able to efficiently translate a ZX-diagram back into a quantum circuit of comparable size. While several sufficient conditions are known for describing families of ZX-diagrams that can be efficiently transformed back into circuits, it has previously been conjectured that the general problem of circuit extraction is hard. That is, that it should not be possible to efficiently convert an arbitrary ZX-diagram describing a unitary linear map into an equivalent quantum circuit. In this paper we prove this conjecture by showing that the circuit extraction problem is #P-hard, and so is itself at least as hard as strong simulation of quantum circuits. In addition to our main hardness result, which relies specifically on the circuit representation, we give a representation-agnostic hardness result. Namely, we show that any oracle that takes as input a ZX-diagram description of a unitary and produces samples of the output of the associated quantum computation enables efficient probabilistic solutions to NP-complete problems., Comment: 15 pages + 3 page appendix

Due to the lack of sophisticated component libraries for microelectromechanical systems (MEMS), highly optimized MEMS sensors are currently designed using a polygon-driven design flow. The advantage of this design flow is its accurate mechanical simulation, but it lacks a method for an efficient and accurate electrostatic analysis of parasitic effects of MEMS. In order to close this gap in the polygon-driven design flow, we present a customized electrostatic analysis flow for such MEMS devices. Our flow features a 2.5D fabrication-process simulation, which simulates the three typical MEMS fabrication steps (namely deposition of materials including topography, deep reactive-ion etching, and the release etch by vapor-phase etching) very fast and on an acceptable abstraction level. Our new 2.5D fabrication-process simulation can be combined with commercial field-solvers such as they are commonly used in the design of integrated circuits. The new process simulation enables a faster but nevertheless satisfactory analysis of the electrostatic parasitic effects, and hence simplifies the electrical optimization of MEMS.

Intellectual Property (IP) theft is a serious concern for the integrated circuit (IC) industry. To address this concern, logic locking countermeasure transforms a logic circuit to a different one to obfuscate its inner details. The transformation caused by obfuscation is reversed only upon application of the programmed secret key, thus preserving the circuit's original function. This technique is known to be vulnerable to Satisfiability (SAT)-based attacks. But in order to succeed, SAT-based attacks implicitly assume a perfectly reverse-engineered circuit, which is difficult to achieve in practice due to reverse engineering (RE) errors caused by automated circuit extraction. In this paper, we analyze the effects of random circuit RE-errors on the success of SAT-based attacks. Empirical evaluation on ISCAS, MCNC benchmarks as well as a fully-fledged RISC-V CPU reveals that the attack success degrades exponentially with increase in the number of random RE-errors. Therefore, the adversaries either have to equip RE-tools with near perfection or propose better SAT-based attacks that can work with RE-imperfections.

We present a completely new approach to quantum circuit optimisation, based on the ZX-calculus. We first interpret quantum circuits as ZX-diagrams, which provide a flexible, lower-level language for describing quantum computations graphically. Then, using the rules of the ZX-calculus, we give a simplification strategy for ZX-diagrams based on the two graph transformations of local complementation and pivoting and show that the resulting reduced diagram can be transformed back into a quantum circuit. While little is known about extracting circuits from arbitrary ZX-diagrams, we show that the underlying graph of our simplified ZX-diagram always has a graph-theoretic property called generalised flow, which in turn yields a deterministic circuit extraction procedure. For Clifford circuits, this extraction procedure yields a new normal form that is both asymptotically optimal in size and gives a new, smaller upper bound on gate depth for nearest-neighbour architectures. For Clifford+T and more general circuits, our technique enables us to to `see around' gates that obstruct the Clifford structure and produce smaller circuits than naive 'cut-and-resynthesise' methods., Comment: 18 pages + appendices with examples, proofs, and pseudocode

A high degree of automation is required when facing full-IC reverse engineering. In this paper, we present a methodology to delayer the chip, acquire SEM images of each layer, obtain the three-dimensional layer reconstruction, and generate a vectorized file in GDSII format for further automatic netlist extraction. A custom software tool named GDS-X has been developed to perform all the required steps from image acquisition to the GDSII file generation. Applying a novel tile mosaicking strategy and using state-of-the-art machine learning techniques for image segmentation, this software reduces dramatically the time required to complete these procedures while minimizing errors compared to old manual reverse engineering techniques.

In the field of computer vision, local binary pattern (LBP) is one of the most popular feature extraction method and has been used in many object detection frameworks. To efficiently extract LBP features in high-resolution images, hardware architecture is needed to disperse CPU burden and to improve the entire object detection performance. In this paper, a hardware implementation of an approximated LBP method with adjustable parameters is introduced. For simulation, Taiwan Semiconductor Manufacturing Company $0.18~\mu \text{m}$ technology is used to implement the LBP hardware, and the hardware can achieve 500 MHz with lower gate count than previous study. The proposed LBP circuit is applied to the pedestrian classification application and the evaluation results show that the approximated LBP values generated by our circuit can achieve comparable classification accuracy with the primitive LBP method. Additionally, the proposed LBP hardware provides adjustable parameters to fit different applications while requires fewer hardware costs as compared with the existing work.

Automated analog circuit design is promising for increasing the design productivity and narrowing the time-to-market, but is facing the bottleneck of tremendous design complexity. In this paper, a simulation-based optimization approach named smart-multiple starting point (MSP) is proposed for analog circuit synthesis. The proposed smart-MSP is based on the framework of MSP optimization, which is shown to be much more efficient than other global optimization methods like simulated annealing, genetic algorithm, particle swarm optimization, etc. Efficient techniques including heuristic-biased starting point selection, sparse regression and probabilistic TABU are developed in smart-MSP and make the algorithm quite smart in a way that the overall optimization process is self-adaptive by learning from the previous local searches and can efficiently produce optimal results to approximate the global optimum. Experiments have demonstrated that the proposed smart-MSP is ${2.6-12.5\times }$ faster than the original MSP method, and is $ {1.3-2100\times }$ faster than other state-of-the-art methods.

The paper presents a novel circuit, implemented in the CMOS technology, that allows for sorting analog signals in parallel. The circuit is to be used in neural networks trained in accordance with Neural Gas (NG) learning algorithm implemented in the CMOS technology. The role of the circuit is to determine, for a given learning pattern, the winning neuron as well as its neighbors. The proposed circuit is versatile. It can be also used, for example, in nonlinear filtering of analog signals. It is capable of performing simultaneously several typical nonlinear operations that include Min, Max and median filtering. The circuit offers high accuracy, which means that it is able to distinguish signals which differ by a relatively small value. However, the accuracy depends on the calculation time. For example, to be able to distinguish the signals that differ by 10 nA (for maximum range of 10 µ A), the assumed calculation time has to be set to at least 1 µ s. To improve the accuracy to 5 nA, the calculation time has to be doubled. The circuit provides us the sorted list of signals, in accordance with their values. This information contains both the positions of the signals on the sorted list and their values. The first parameter is used in the NG learning algorithm. The circuit was implemented in the TSMC 180 nm CMOS technology and verified by means of the corner analysis in the HSpice environment. For an example case of eight inputs varying in between 1 to 10 µ A the circuit dissipates an average power of 300 µ W, at data rate of million sorting operations per second.

In this paper, an analytical coupling matrix extraction scheme is proposed for parallel-connected dual-passband coupled-resonator filters for the first time. Model-based vector fitting technique is adopted to fit the measured responses of the dual-passband filter (DPBF) with a set of rational functions, from which a transversal coupling matrix can be constructed. A novel coupling matrix transformation strategy is developed to transform the transversal coupling matrix to the one corresponding to the topology of a parallel-connected DPBF. A practical filter is used as a test example to demonstrate the extraction procedure. In diagnosing the coupling matrix of the test filter, two kinds of ambiguity problems are discussed in detail and are solved by a perturbation technique. This paper provides a general theoretic framework for computer-aided tuning of a parallel-connected dual-passband or multiple-passband filter.

In this paper, a unified floating immittace emulator based on Current Conveyor Transconductance Amplifier (CCTA) is put forward. It uses two CCTAs, two additional components (two MOS based resistors/one capacitor and one MOS based resistor) and four MOS switches. It can realize both positive and negative floating immittances through appropriate setting of switches. The proposed topology does not require any component matching, thus making it suitable for integration viewpoint. Further, the immittance may be tuned electronically via bias current of CCTA. Additionally, the operation in fractional domain also investigated. The impact of parasitics of CCTA on the performance of the proposed circuit is mathematically formulated. The functionality of the proposed circuit is verified through post layout simulations carried out using the netlist extraction from the layout and examined through SPICE simulations using 90 nm process parameter. The area of the layout of proposed unified immittance emulator is 67.80 μm × 22.80 μm. The proposed immittance circuit is used to implement notch filter, fifth order low pass filter, and capacitance cancellation circuit.

We have proposed a transmission system of the additional data by using frequency modulation technique. In a receiver, demodulation characteristics deteriorate according to data speed. In the previous work, we showed the emphasis technique can reduce the degradation in demodulated signal. In this paper, we designed the delay detection circuit on the basis of the detailed analysis. To investigate the proposed circuit, we fabricated the delay detection circuit with emphasis using 65-nm CMOS process. We confirmed the improved linearity in demodulated signal, which indicate our proposed circuit can be applicable to the 10-Gb/s demodulating systems.

Performance optimization as per the desired specifications is a major requirement of analog and mixed signal circuit design process. Rapid scaling of the semiconductor technology demands efficient optimization techniques with minimal manual efforts. In this paper, a gradient based method for analog circuit optimization using adjoint network based sensitivity analysis is presented. The sensitivity of circuit response with respect to the different parameters is computed by using analog circuit and its adjoint transformation. The proposed method is applied to optimize performance of a two stage operational amplifier (OpAmp). Subsequently, the OpAmp circuit is simulated using Cadence Virtuoso for optimized parameters and the results are validated with post fabrication measurement results.

Purpose This paper aims to design a new bandgap reference circuit with complementary metal–oxide–semiconductor (CMOS) technology. Design/methodology/approach Different from the conventional bandgap reference circuit with operational amplifiers, this design directly connects the two bases of the transistors with both the ends of the resistor. The transistor acts as an amplifier to amplify the change of voltage, which is convenient for the feedback regulation of low dropout regulator (LDO) regulator circuit, at last to realize the temperature control. In addition, introducing the depletion-type metal–oxide–semiconductor transistor and the transistor operating in the saturation region through the connection of the novel circuit structure makes a further improvement on the performance of the whole circuit. Findings This design is base on the 0.18?m process of BCD, and the new bandgap reference circuit is verified. The results show that the circuit design not only is simple and novel but also can effectively improve the performance of the circuit. Bandgap voltage reference is an important module in integrated circuits and electronic systems. To improve the stability and performance of the whole circuit, simple structure of the bandgap reference voltage source is essential for a chip. Originality/value This paper adopts a new circuit structure, which directly connects the two base voltages of the transistors with the resistor. And the transistor acts as an amplifier to amplify the change of voltage, which is convenient for the feedback regulation of LDO regulator circuit, at last to realize the temperature control.

In this paper, an inherently fail-safe electronic logic circuit is proposed. Further, the logic is investigated for safety critical application in a nuclear power plant with a very low unsafe failure probability requirement. The application involves control circuit for operation of solenoid valves based on the plant state, wherein the de-energization of certain solenoid valves is considered as a safe state. The inherent fail-safeness is achieved by processing the inputs as synchronized pulses rather than static digital levels. Pulse transformers are used at specific locations in the circuit so that energy transition to subsequent stages of the circuit is seized in case of a failure in the previous stage. Such pulse processing is selectively applied to those parts of the circuit for which fail-safe behavior of final control elements is expected. A Failure Mode Effect Analysis (FMEA) is performed for the circuit to systematically ensure that failure of components in postulated modes will result in the fail-safe state. A prototype circuit is built to verify the results obtained from FMEA. The inherency in the circuit is shown to possess a very low unsafe failure probability and quantitatively it is shown. The proposed technique is suggested as a diverse method to control, redundant instrumentation provisions usually provided for safety critical application. This method can be easily extended to similar industrial control involving combinational circuits with modifications.

In this paper, a resynthesis technique is introduced in order to reduce the Soft Error Rate (SER) of combinational circuits. This technique is based on the circuit partitioning and a local logical replacement. The proposed method provides an innovative approach to maximize the logical masking probability of the circuit gates. In this technique, the circuit is divided into a set of small sub-circuits. Different logical implementations of sub-circuits with the same function which satisfy the circuit timing and area constraints are carried out using a AND-INV Graph (AIG) scheme. Then, an implementation of each sub-circuit that provides the maximum logical masking and minimum transient faults generation probability is used in place of the current sub-circuit in the main circuit. In order to choose the best alternative among the different implementations of a sub-circuit (i.e. the one that provides the maximum circuit SER reduction), a new metric called Global Failure Probability (GFP) is introduced. The proposed parameter evaluates the contribution of different implementations of sub-circuits in total circuit SER. Using GFP to assess the effect of different implementations of a sub-circuit in the circuit SER avoids estimating the total circuit SER repeatedly during SER optimization process that is very time consuming. Simulation results based on ISCAS benchmark circuits show that, on average, a circuit failure reduction of 23.4% is achieved compared to the original one; where the average area overhead and delay overhead is 8.72% and 5.63% of the original circuit, respectively. The results also show that the proposed method is 77.8× faster compared to simulation based method [6].

PurposeLack of optimization and improvement on experimental circuits precludes comprehensive statements. It is a deficiency of the existing chaotic circuit technology. One of the aims of this paper is to solve the above mentioned problems. Another purpose of this paper is to construct a 10 + 4-type chaotic secure communication circuit based on the proposed third-order 4 + 2-type circuit which can output chaotic phase portraits with high accuracy and high stability.Design/methodology/approachIn Section 2 of this paper, a novel third-order 4 + 2 chaotic circuit is constructed and a new third-order Lorenz-like chaotic system is proposed based on the 4 + 2 circuit. Then some simulations are presented to verify that the proposed system is chaotic by using Multisim software. In Section 3, a fourth-order chaotic circuit is proposed on the basis of the third-order 4 + 2 chaotic circuit. In Section 4, the circuit design method of this paper is applied to chaotic synchronization and secure communication. A new 10 + 4-type chaotic secure communication circuit is proposed based on the novel third-order 4 + 2 circuit. In Section 5, the proposed third-order 4 + 2 chaotic circuit and the fourth-order chaotic circuit are implemented in an analog electronic circuit. The analog circuit implementation results match the Multisim results.FindingsThe simulation results show that the proposed fourth-order chaotic circuit can output six phase portraits, and it can output a stable fourth-order double-vortex chaotic signal. A new 10 + 4-type chaotic secure communication circuit is proposed based on the novel third-order 4 + 2 circuit. The scheme has the advantages of clear thinking, efficient and high practicability. The experimental results show that the precision is improved by 2-3 orders of magnitude. Signal-to-noise ratio meets the requirements of engineering design. It provides certain theoretical and technical bases for the realization of a large-scale integrated circuit with a memristor. The proposed circuit design method can also be used in other chaotic systems.Originality/valueIn this paper, a novel third-order 4 + 2 chaotic circuit is constructed and a new chaotic system is proposed on the basis of the 4 + 2 chaotic circuit for the first time. Some simulations are presented to verify its chaotic characteristics by Multisim. Then the novel third-order 4 + 2 chaotic circuit is applied to construct a fourth-order chaotic circuit. Simulation results verify the existence of the new fourth-order chaotic system. Moreover, a new 10 + 4-type chaotic secure communication circuit is proposed based on chaotic synchronization of the novel third-order 4 + 2 circuit. To illustrate the effectiveness of the proposed scheme, the intensity limit and stability of the transmitted signal, the characteristic of broadband and the requirements for accuracy of electronic components are presented by Multisim simulation. Finally, the proposed third-order 4 + 2 chaotic circuit and the fourth-order chaotic circuit are implemented through an analog electronic circuit, which are characterized by their high accuracy and good robustness. The analog circuit implementation results match the Multisim results.

Optical proximity correction (OPC) is invaluable to precise layout manufacturing in the advanced nanometer technologies. However, lack of research activity on OPC for analog integrated circuits has currently led to sole dependence on digital solutions. In this paper, we propose a rule-based OPC (RB-OPC) methodology with process variation (PV) consideration, which is integrated into an analog layout migration process. Based on the unique features of analog layouts, the accuracy limitation of RB-OPC is compensated by local wire widening and wire shifting operations during layout migration. Moreover, innovative PV-band shifting is deployed to preserve analog circuit performance against PV. According to our experimental results, the proposed analog layout migration with PV-aware RB-OPC can achieve much higher efficiency with an even lower mask complexity and an acceptable edge placement error compared to some well-known commercial and academic digital solutions. The circuit performance by using our proposed methodology is also better than that from alternative methods in the mismatch scenarios due to our special PV-band handling on transistor gates.

With advancing process technologies and booming Internet of Things markets, millimeter-wave CMOS RFICs have evolved rapidly and been widely applied in recent years. The performance of CMOS RFICs is very sensitive to the chip layout, and a tiny variation of the microstrip length can cause a large impact to the circuit performance. This results in a time-consuming tuning process including much simulation effort for chip design, which becomes the major bottleneck for time to market. This paper introduces a progressive integer-linear-programming-based method consisting of two phases: 1) global layout generation and 2) iterative validation. In the global layout generation phase, we focus on the most critical constraints such as layout planarity and device connection relations to determine the topology of the final design. This provides a basis for constructing the accurate model in the iterative validation phase. The layouts generated by applying our method can satisfy very stringent routing requirements of microstrip lines, including spacing/noncrossing rules, precise length, and bend number minimization, within a given layout area. The resulting RFIC layouts excel in both performance and area with much fewer bends compared with the simulation-tuning based manual layout, while the layout generation time is significantly reduced from weeks to a few minutes.

This paper presents a solution for battery-less power management circuits for micro-power energy converters, allowing energy harvesting systems to operate under continuous and intermittent conditions. The proposed trigger circuit is a fully passive, normally open, single pole, single throw, analog switch driven by a nano-power CMOS control unit. The trigger circuit starts in an OPEN state until the voltage, at its input terminal, reaches a high threshold, when it toggles to the CLOSED state. Once the input voltage drops below a low threshold, the trigger circuit returns to the OPEN state. In the CLOSED state, the trigger circuit creates a low resistance path between the input and output terminals, while at the OPEN state the input is isolated from the output. A first prototype was breadboarded by using discrete components for the sake of performance evaluation. Low threshold voltages (2.15 V and 1.15 V), sub-ohm CLOSED-state resistance, and power consumption requirements (in the order of 55.9 and 167.7 nW), coupled with relatively high energy extraction capabilities are confirmed by experimental results. These features put our proposed circuit among the best of its kind in the state-of-the-art circuits. To prove the effectiveness of the proposed trigger circuit, we have included it into a custom battery-less power management circuit for a piezoelectric energy harvesting system. The system was proven to work even under intermittent operating conditions, and lock-up phenomena, related to current surge effect, were avoided. This publication was made possible by NPRP grant # 6-203-2-086 from the Qatar National Research Fund (a member of Qatar Foundation). The statements made herein are solely the responsibility of the authors. Scopus

In the post-CMOS scenario, field coupled nanotechnologies represent an innovative and interesting new direction for electronic nanocomputing. Among these technologies, nanomagnet logic (NML) makes it possible to finally embed logic and memory in the same device. To fully analyze the potential of NML circuits, design tools that mimic the CMOS design-flow should be used for circuit design. We present, in this paper, the latest and improved version of Torino Politecnico Nanotechnology (ToPoliNano), our design and simulation framework for field coupled nanotechnologies. ToPoliNano emulates the top-down design process of CMOS technology. Circuits are described with a VHSIC hardware description language netlist and layout is then automatically generated considering in-plane NML (iNML) technology. The resulting circuits can be simulated and performance can be analyzed. In this paper, we describe several enhancements to the tool itself, like a circuit editor for custom design of field coupled nanodevices, improved algorithms for netlist optimization and new algorithms for the place and route of iNML circuits. We have validated and analyzed the tool by using extensive metrics, both by using standard circuits and ISCAS’85 benchmarks. This contribution highlights the improvements of ToPoliNano, which is now a innovative and complete tool for the development of iNML technology.

A new method for computer-aided analysis of differential mode input filters is presented in this paper, aiming to compute in an efficient manner input current spectra of switching converters in a wide frequency range. The method is intended to facilitate computer-aided design of input filters, and it is based on simulation of accompanying averaged circuit and superimposing the switching ripple to the averaged waveforms. A method to derive a continuous-time averaged circuit model is described. To obtain the model, the converter is partitioned into a circuit part, characterized by equations common for describing electric circuits, and a modulator part, which generates duty ratio functions. Three modulation methods are described, and superposition of associated switching ripple is formalized for each of them. The method is illustrated in simulation of two converters on the design of their input filters.

In this brief, a nonlinear integrated circuit to harvest different types of digital computation from complex dynamics is designed and fabricated. This circuit can be dynamically reconfigured to implement different two-input, one-output digital functions. The main advantage of the circuit is the ability to implement different digital functions in each clock cycle without halting for reconfiguration.

The China high-speed trains use cable trays to neatly arrange the cables running through the distributed systems. On one hand, they protect cables against external electromagnetic interference and reduce external radiation from the cables. On the other hand, the cable trays create waveguide structures that affect the coupling among cables inside the cable trays. To simplify coupling analysis for cables going through a cable tray, a lumped circuit model was built using admittance blocks extracted from a mixed-potential integral equation (MPIE) formulation. In the MPIE formulation, either the half-free space or the waveguide dyadic Green's function was used depending on the region where the cables were. A test case was investigated. Results by the proposed circuit model were validated by measurement and full-wave simulation results.

This paper introduces a methodology able to produce an exact valid and physically meaningful circuit representation out of generic multi-port passive linear state-space models. The proposed method has a strong theoretical relevance as it allows the generation of equivalent netlists whose RLC values are guaranteed positive, without applying any additional approximations, and based only on coordinate transformations and circuit laws interpretation. In this sense it can be viewed as a generalization of Foster's synthesis that is guaranteed to produce a circuit description containing only elements with physical meaning. In addition, it also presents pratical advantages, as it generates a very sparse circuit, whose usage is highly efficient within standard simulation and analysis platforms. Furthermore, the synthesized circuit can be easily included in any standard environment for simulation, verification, delay calculation, symbolic analysis, etc., and in combination with other models for system-level detailed simulation, which further increases the practical relevance of the proposed approach.

Analog integrated circuit sizing can be modeled as an optimization problem and solved by optimization heuristics. The resulting solution is dependent on the modeling strategy and on the performance estimation, which is done, in general, by electrical simulations. However, the optimized solution falls on the border of the design space, where a small variation in the device parameters affects the circuit performance. In order to address this issue during sizing steps, a Monte Carlo simulation is included in the optimization loop, leading in a computational effort increasing. This work analyses both Latin Hypercube and the traditional random sampling methods in order to reduce the number of Monte Carlo runs for minimizing the necessary time to estimate the resulting yield at each iteration of the optimization process. Based on these analysis a hybrid sampling method is proposed to lower the Monte Carlo processing time. The methodology is applied for the sizing of a two-stage Miller operational transconductance amplifier, showing advantages in terms of processing time and circuit performance while producing a more efficient search in the design space.

Objectives: To design and study a fourth order Bubble error correction circuit for a Flash Analog to Digital Converter by making use of a Multiplexer based encoder. Methods/Statistical Analysis: A Thermometer to binary encoder acts as a vital element in the functioning of flash ADCs. Output of flash ADCs is in thermometer code. Ideally, Thermometer code shows single transition but in case of clock jitter and device mismatch, multiple transitions take place introducing bubbles in the code. This error leads to inaccurate encoding process. A Bubble error correction circuit has been proposed that eliminates bubble error upto fourth order as compared to existing circuit that eliminated error only upto third order. Simulation shows the transistor requirement of existing and proposed circuit is same thus making present circuit more efficient and acceptable. Findings: The Number of transistors required in different types of encoders can be understood through the tables. Although ROM based encoder along with BEC circuit requires 714 transistors which is less than other circuits. But since the conversion speed of ROM based encoder is relatively slow and because of constant static current which is used for presetting the encoder, the power consumption goes high and so ROM based encoder is avoided. Wallace tree requires lesser transistors but is unsuitable for the high speed of operations. Fat tree encoder along with BEC circuit requires 832 transistors. It has slightly less transistor requirement than proposed circuit but its difficult layout prevents us from using it. All the three encoder types mentioned in the table namely ROM based, Wallace tree and fat tree encoders are capable to remove bubble error only upto 3rd order. In case designing is done to remove higher order bubble error considers it to be fourth then definitely the transistor count will increase. However our proposed BEC circuit with MUX based encoder eliminates bubble error upto fourth order. It can be seen from the table ,the transistor count in new BEC circuit for removing fourth order error nearly matches the transistor count for removal of third order error by remaining encoders. Thus existing circuits and proposed circuit will have much difference in their efficiency of operation. Lesser number of transistor requirements makes our circuit more acceptable and efficient. Application/Improvements: Varying the (W/L) ratio may contribute in bringing changes in the delay and the average power dissipation making the circuit more efficient. CMOS inverter is susceptible to the process and the temperature variation. Temp variation would make the threshold voltage change so we may use another design whose comparator uses a self tuned inverter.

In this paper, a novel matching circuit design method utilizing a genetic algorithm (GA) and the measured S-parameters of randomly moved coil configurations is discussed. Through the detailed comparison of different matching circuit topologies, the superiority of active matching circuits is clearly demonstrated, and potentially there is 21.4% improvement in the wireless power transfer efficiency by using a four-cell active matching circuit, which can create 16 different impedance values. Also, the matching circuit design simulation can be further simplified by choosing a much smaller subset of representative impedance values for the utilized time-changing coil configuration through the employment of $k$ -means clustering and use only these values for the derivation of the optimal matching circuit. This heuristic approach could drastically reduce the time for the matching circuit design simulation, especially for matching circuit topologies with a larger number of cells.

The signal distribution interconnect network modeling plays an important role during the digital/mixed printed circuit board (PCB) design. With the increase of the design complexity, the PCB interconnect modeling becomes a challenging task. This paper proposes an innovative circuit theory of the PCB electrical interconnects modeling based on the tensorial analysis of network (TAN). The model under study, fundamentally built with the Kron–Branin formalism, is applied to the asymmetrical 1:3 Y-Y-tree interconnects. This Kron–Branin method enables to establish quickly the tree interconnects equivalent model for the signal integrity (SI) analysis. An asymmetrical microstrip circuit was designed and fabricated to validate the developed TAN concept. The modeled, simulated, and measured S-parameters are in good agreement in the broad frequency band 0.1 MHz to 8 GHz. The electrical power budget distributed through the Y-Y-tree prototype in dc and in the considered entire frequency band was analyzed. Furthermore, the Kron–Branin model was also validated in the time domain with 1-Gb/s-rate 8-bits serial data and eye diagram analyses. This innovative formalism presents a considerably high computation speed and is beneficial for the SI analyses thanks to its adaptability to the complex system.

In the field of analog integrated circuit (IC) design, small-signal macromodels play indispensable roles for developing design insight and sizing reference. However, the subject of automatically generating symbolic low-order macromodels in human readable circuit form has not been well studied. Traditionally, work has been published on reducing full-scale symbolic transfer functions to simpler forms but without the guarantee of interpretability. On the other hand, methodologies developed for interconnect circuits (mainly resistor-capacitor-inductor (RCL) networks) are not suitable for analog ICs. In this work, a topological reduction method is introduced that is able to automatically generate interpretable macromodel circuits in symbolic form; that is, the circuit elements in the compact model maintain analytical relations of the parameters of the original full circuit. This type of symbolic macromodel has several benefits that other traditional modeling methods do not offer: First, reusability, namely that designer need not repeatedly generate macromodels for the same circuit even it is re-sized or re-biased; second, interpretability, namely a designer may directly identify circuit parameters (in the original circuit) that are closely related to the dominant frequency characteristics, such as dc gain, gain/phase margins, and dominant poles/zeros. The effectiveness and computational efficiency of the proposed method have been validated by several operational amplifier (opamp) circuit examples.

Current technology scaling trends aggressively increases the susceptibility of combinational circuit reliability to radiation-induced transient faults (which also known as soft errors). Various gate sizing techniques have been used to reduce soft error rate (SER) in the past, but their main drawback is that they are expensive in term of run time. These methods require changes to adapt to the large scale circuits. In this paper, an efficient circuit partitioning-based gate sizing method is presented, which significantly speeds up the gate sizing optimization process. In the proposed method, the circuit is divided into the topologically levelized small subcircuits by cone structures. Then, the subcircuits which are located in the same level are resized individually and independently. The subcircuit error probability (SEP) metric is introduced to evaluate the contribution of each subcircuit into the total circuit SER. The key idea of the proposed method is to evaluate the effects of each gate sizing on circuit reliability locally using SEP instead of global evaluation by the total circuit SER. Such evaluation results in speeding up the gate sizing optimization process. Experimental results show that the proposed approach is about 280× orders of magnitude faster than the sensitivity-based gate sizing approach [R. R. Rao, D. Blaauw, and D. Sylvester, “Soft error reduction in combinational logic using gate resizing and flipflop selection,” in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des. , 2006, pp. 502–509] while it can achieve up to 45% reduction in circuit SER with less than 17% area overhead. This level of speed and efficiency makes the proposed approach a viable solution to mitigate the SER of very large combinational circuits used in industry.

This paper is concerned with circuit implementation in reaction-diffusion neuron model. Firstly, in order to realize easily, one obtains the equivalent form by discretization of this neuron model. In the frame of discrete model, every parameter can be represented by the basic circuit component. Then the digital programmable transconductance amplifier (DPTA) is designed to realize the digitally function in circuit. In addition, the DPTA is applied to realize two activation functions and the simulation results are verified in Multisim.

A novel photonic integrated circuit architecture for implementing orthogonal frequency division multiplexing by means of photonic generation of phase-correlated sub-carriers is proposed. The circuit can also be used for implementing complex modulation, frequency up-conversion of the electrical signal to the optical domain and frequency multiplication. The principles of operation of the circuit are expounded using transmission matrices and the predictions of the analysis are verified by computer simulation using an industry-standard software tool. Non-ideal scenarios that may affect the correct function of the circuit are taken into consideration and quantified. The discussion of integration feasibility is illustrated by a photonic integrated circuit that has been fabricated using library' components and which features most of the elements of the proposed circuit architecture. The circuit is found to be practical and may be fabricated in any material platform that offers a linear electro-optic modulator such as organic or ferroelectric thin films hybridized with silicon photonics.

This paper discusses the electrochemical modeling of a microphotosynthetic power cell ( µ -PSC) in a similar way as the conventional fuel cell model while taking into consideration the electrochemical dynamics of the chemical contents of the cell. It also presents the development of an electrical equivalent circuit that represents the operation of the fabricated cell. The developed equivalent circuit is different from previous works in which they used the equivalent circuit of an ordinary solar cell. The proposed model predicts the performance of this type of power harvesting cell. The study includes the steady-state and transient responses when the cell is connected to an external load. In particular, the focus of this paper is related to the development of an electrical representation with a computationally efficient parameter model for real-time simulation and control. The performance of this model is simulated and results are evaluated and compared with experimental data.

Fast switching and large capacity in modern power converters generate large-voltage peak during the diode's reverse-recovery process. Being different from the steady-state reverse recovery, short-time freewheeling of diodes at higher speed switching may generate higher reverse-recovery voltage peak. In this paper, the reverse recovery of p-i-n diodes under short-time freewheeling in a typical power converter circuit is studied with considerations of different initial current of the related IGBTs. By establishing the boundary connections between the turn-on and the turn-off transient stages, a mixed model of the diode's reverse-recovery voltage peak under short-time freewheeling is finally obtained, which combines the physics-based model with the behavior model. Model parameters were then extracted through measurements and circuit extraction methods to relax the complexity. Experiments were performed in a half-bridge inverter unit with 1200-V/50-A IGBTs and p-i-n freewheeling diodes at different short freewheeling time. The accuracy of the proposed model is verified by comparing the simulated waveforms with the measured data. The influence of different initial current on the voltage peak at short-time freewheeling was also evaluated using the proposed model.

A current-mode State-Controlled Cellular Neural Network (SC-CNN) cell based on current conveyors (CCIIs) and multi-output current conveyors (MOCCII) is presented in this paper. Different from the voltage-mode SC-CNN cell whose state variable is voltage signal, the current-mode SC-CNN cell takes current signal as its state variable. A current-mode SC-CNN-based chaotic circuit is developed by using the suitable connection of three current-mode SC-CNN cells. When compared with the existing voltage-mode chaotic circuits, the proposed current-mode chaotic circuit can operate at higher frequency ranges. In addition to this, state currents can be directly obtained at high impedance outputs of MOCCIIs. Furthermore, all elements in this circuit are grounded, thus it is very suitable for integrated circuit (IC) fabrication. Pspice simulations are given to demonstrate the dynamical behaviors of the proposed circuit and its high frequency performance.

Developing simple, economic, and efficient electrical power conversion systems for wave energy converters (WECs) is an on-going research topic. This paper considers a simple resonance circuit to maximise the ac-dc power conversion of a permanent magnet linear generator (PMLG). To implement this circuit, the PMLG model parameters were obtained. In this paper, we developed a procedure for designing a two-sided planar PMLG considering the corresponding physical parameters. For this method, we set the basic parameters and calculated the derived parameters for the PMLG. The resonance circuit was composed of a three-phase rectifier with a shunt connection of capacitors between its diodes. The value of the capacitors was calculated using the resonance principle at a specific dominant frequency obtained from the location of the WEC installation. We compared the performance of the proposed resonance circuit with that of an existing resonance circuit. The proposed circuit generates more power, requires fewer components, and presents fewer harmonics. In addition, a higher-quality damping force was obtained when using the PMLG connected to the proposed resonance circuit and a resistive load.

As the fundamental technology of autonomous vehicles and high-speed tracking, high-speed vision always suffers from the bottlenecks of on-chip bandwidth and storage due to the resource constraints. To improve the resource efficiency, we propose a hardware-efficient image compression circuit based on the vector quantization for a high-speed image sensor. In this circuit, a self-organizing map is implemented for the on-chip learning of codebook to flexibly satisfy the requirements of different applications. To reduce the hardware resources, we present a reconfigurable complete-binary-adder-tree, where the arithmetic units are reused completely. In addition, a mechanism of partial vector-component storage is adapted to make the compression ratio adjustable. Finally, a parallel-elementary-stream design ensures a high processing speed. The proposed circuit has been implemented on the field-programmable gate araray and also applied in a high-speed object tracking system. The experimental results indicate that it achieves an encoding speed of 722 frames/s with 128 weight vectors when working at 79.8 MHz, and the worst tracking error caused by the proposed circuit is merely 9 pixels. These results evince that our proposed circuit can be completely integrated with a high-speed image sensor and used in high-speed vision systems.