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Proposed here is a new approach for synthesizing an internal model control (IMC) anti-windup (AW) compensator for a stable plant subject to input saturation. Built on the conventional IMC AW scheme, which preserves the stability robustness of the unconstrained system, the proposed linear AW compensator improves the performance of the constrained system. The analysis conducted through the loop decomposition of the AW system clearly reveals the impacts of the AW compensator on the closed-loop stability and performance. Loop shaping techniques are executed to design the AW compensator. The effectiveness of this approach is demonstrated using a numerical example. [DOI: 10.1115/1.4000664]

This paper proposes a method for optimal placement of phasor measurement units (PMUs) for complete observability of a power system for normal operating conditions, as well as for single branch outages. A binary search algorithm is used to determine the minimum number of PMUs needed to make the system observable. In case of more than one solution, a strategy is proposed to select the solution resulting in the most preferred pattern of measurement redundancy. The proposed method is used to benchmark the optimal PMU placement solutions for the IEEE 14-bus, IEEE 24-bus, IEEE 30-bus and New England 39-bus test systems. The proposed method is applied on a 298-bus system to determine the optimal placement of PMUs when conventional measurements are available. Index Terms--Benchmarking, exhaustive search, measurement redundancy, observability, optimal placement, phasor measurement units, state estimation.

This paper describes the observation of pulse shortening in an 11.4-GHz magnicon amplifier due to competition with a parasitic gyrotron mode. This effect was observed following the installation of a new electron beam collector. The parasitic mode occurred only at high operating powers, when the beam transverse momentum was high, and the growth of the parasitic mode caused the power in the output pulse to drop substantially. We analyze the competition between the gyrotron and magnicon modes in the output cavity using a time-dependent multimode gyrotron simulation code that has been specially modified to model competition between synchronous magnicon and nonsynchronous gyrotron interactions, and compare the results to experimental observations. We also analyze the effect due to the change in the collector. Index Terms--Electron devices, gyrotron, magnicon, microwave amplifier, parasitic mode.

An axially symmetric power combiner, which utilizes a tapered conical impedance matching network to transform ten 50-[Uhm] inputs to a central coaxial line over the X-band, is presented. The use of a conical line allows standard transverse electromagnetic design theory to be used, including tapered impedance matching networks. This, in turn, alleviates the problem of very low impedance levels at the common port of conical line combiners, which normally requires very high-precision manufacturing and assembly. The tapered conical line is joined to a tapered coaxial line for a completely smooth transmission line structure. Very few full-wave analyses are needed in the design process since circuit models are optimized to achieve a wide operating bandwidth. A ten-way prototype was developed at X-band with a 47% bandwidth, very low losses, and excellent agreement between simulated and measured results. Index Terms--Combiners, conical combiners, conical transmission lines, N-way splitters, passive components, radial combiners, tapered lines.

This paper discusses the formulation of 'silicon mimetic' mixed-signal integrated circuit (IC) models for biocellular genetic circuits and state machines that utilize the rich variety of deoxyribonucleic acid and protein regulatory interactive pathways. A novel mixed-signal circuit model is reported for determining the state transitions of a genetic circuit. Using hysteretic electronic switch analogues for messenger ribonucleic acid transcription, a genetic state machine can be auto-triggered resulting in the self-timed transformation of an existing state of gene expression into another desired state of gene expression. Such an electronic model of genetic circuits and state machines focuses on the central theme of post-genomic research into gene-protein connectivity based cellular phenomenon. Novel synthetic genetic circuits designed using the mature resources of IC simulation will result in important outcomes for biomaterials based computation, bionanotechnology, as well as, gene and cell therapy. Index Terms--Gene-protein connectivity, genetic circuits, integrated circuits (ICs), modeling, messenger ribonucleic acid (mRNA) transcription.

In switched-mode power supplies--the predominant type of power converter in contemporary electronic equipment--ferrite magnetic components under dc bias conditions are typically large and have relatively high losses. The nature of these losses is not widely understood, and research in this area has been hampered by the difficulty of obtaining accurate core loss measurements. This paper reviews previous studies on the nature of core losses under dc bias, and presents new results, measured by a technique that has not previously been utilized for the measurement of core losses under dc bias conditions. The results show that ferrite core losses increase significantly with an increasing dc bias, and highlight the need for further research over a wider range of conditions to fully characterize the phenomenon. Index Terms--Core losses, ferrite, switched-mode power supply.

This brief proposes lower power lower delay design for CMOS tapered buffers. A slight increase in the threshold voltage is shown to have an exponential effect in reducing the total power dissipation. The corresponding increase in the propagation delay is compensated for by increasing the number of buffer stages such that there is still an overall significant reduction in the total power dissipation. As compared to the constant threshold voltage design based on a cost function of P[T.sup.2], the proposed scheme can lead to either a power dissipation reduction of about 70 % while maintaining the same delay, or up to 30% in power dissipation with 10% propagation delay reduction, respectively, in 65-nm technology with [V.sub.DD] = 1 V, minimum size gate capacitance, [C.sub.g] = 1.5 fF, and minimum size output capacitance, Co = 1 fF. Closed-form expressions that give the optimum threshold voltage and number of stages are presented. Index Terms--Buffers, circuits, circuit optimization propagation delay, dynamic power, leakage power, short-circuit power.

Charge collection efficiency (CCE) generated in a 6H-SiC [p.sup.+]n diode by impact of heavy ions was evaluated by the transient ion beam induced current (TIBIC) technique. Numerical analysis by using technology computer aided design (TCAD) concludes that the Auger recombination process reduces CCE. Comparing experimentally measured CCEs with calculated ones revealed that the ambipolar Auger coefficient of about 3 x [10.sup.-29][cm.sup.6]/s. Index Terms--6H-SiC diode, auger recombination, CCE, PHD, TCAD, TIBIC system.

Multiphase is an old technique that, nowadays, is widely used in several dc-dc applications such as voltage regulator module and automotive. The number of phases is usually kept relatively low (three or four) in most cases. However, the advantages of multiphase converters (mainly the reduction of input and output filters with its associated increase in maximum control bandwidth) grow with the number of phases in the ideal case. This growth is limited by nonidealities, mainly the tolerances of components (semiconductors and inductors). The purpose of this paper is to evaluate the effect of tolerances of the inductance on the current ripple. This nonldeality causes the loss of two important advantages of multiphase converters, such as very high frequency and very low amplitude current ripple. The use of digital control can help to reduce drastically this problem. A simple algorithm, based on changing the triggering sequence of the phases, allows a big reduction of the impact of this nonideality. Experiments are included in the paper. Index Terms--Current balance, current ripple, digital control, inductor tolerance, multiphase converters.

A modification of the Wilkinson power divider is presented that eases planar implementation while maintaining performance. By adding transmission lines between the resistor and the quarter-wave transformers of the traditional design, a range of valid solutions exists that meet the conditions of being reciprocal, isolated between the output ports, and matched at all ports. The proposed design is particularly useful at millimeter-wave frequencies where reduced physical dimensions make a circuit configuration suitable for low-cost package-level implementation difficult using traditional methods. Two frequency bands are demonstrated. At V-band, the circuit gives 0.3-dB excess insertion loss, 19-dB isolation, and 50% bandwidth. At the W-band, the circuit gives 0.75-dB excess insertion loss, 24-dB isolation, and 39% bandwidth. Index Terms--Balun, hybrid, millimeter-wave circuits, power divider, Wilkinson power divider.

In this paper, a new power divider concept, which provides high flexibility of transmission line characteristic impedance and port impedance, is proposed. This power divider is implemented on a parallel-strip line, which is a balanced transmission line. By implementing the advantages and uniqueness of the parallel-strip line, the divider outperforms the conventional divider in terms of isolation bandwidths. A swap structure of the two lines of the parallel-strip line is employed in this design, which is critical for the isolation enhancements. A lumped-circuit model of the parallel-strip swap including all parasitic effects has been analyzed. An equal power divider with center frequency of 2 GHz was designed to demonstrate the idea. The experimental results show that the equal power divider has 96.5% -10-dB impedance bandwidth with more than 25-dB isolation and less than 0.7-dB insertion loss. In order to generalize the concept with an arbitrary power ratio, we also realize unequal power dividers with the same isolation characteristics. The impedance bandwidth of the proposed power divider will increase with the dividing ratio, which is opposite to the conventional Wilkinson power divider. Unequal dividers with dividing ratios of 1 : 2 and 1 : 12 are designed and measured. Additionally, a frequency independent 180[degrees] power divider has been realized with less than 2[degrees] phase errors. Index Terms--Arbitrary power-dividing ratio, parallel-strip line, ring structure, unequal power divider.

In this paper, a deep bandgap behavior analysis of the vertical cascaded electromagnetic-bandgap (EBG) structure is made. It is shown that the vertical cascaded EBG structure can be decomposed into two EBG structures cascaded horizontally, one with the bigger patches and the other with the smaller patches. The design guidelines of the vertical cascaded EBG structure are drawn. Furthermore, the vertical cascade concept is extended to 3-D cascade for wideband simultaneous switching noise (SSN) suppression. The number of rows of patches for noise coupling reduction is investigated. Building SSN isolation walls along a printed circuit board for wideband electromagnetic-interference reduction and along sensitive devices for SSN isolation using a 3-D cascaded EBG structure is proposed. Simulations and measurements are performed to verify the SSN suppression. High performance is observed. Index Terms--Electromagnetic bandgap (EBG), electromagnetic interference (EMI), high-speed digital circuit, printed circuit board (PCB), simultaneous switching noise (SSN).

A simulation method in which grooves are virtually distributed on the slider air bearing instead of on the grooved medium surface has been developed and used to investigate the performance of sliders flying over the surface of a discrete-track medium. The simulated flying height loss due to a discrete-track medium coincides well with the measured data, whereas the average-estimation method overestimates flying height loss. Among the characteristics of a slider flying over the surface of a discrete-track medium that were studied are the flying attitude, the effect of groove parameters on flying profile, and the flying height losses due to manufacturing variation and altitude. The results indicate that when a slider is flying over the surface of a discrete-track medium, it will have a higher 3[sigma] of flying height, be more sensitive to altitude, and will have a greater flying height loss. [DOI: 10.1115/1.2768069] Keywords: discrete track medium, air bearing slider, head-disk interface, flying height

Defining power components for unbalanced three-phase systems operating under nonsinusoidal conditions is an area of active research which spawned many theories. The approaches may be classified into two groups: the first is a bottom-up approach that extends well accepted definition of power components for single-phase systems operating under ideal sinusoidal situations to the case of unbalanced three-phase systems in nonsinusoidal situations. The second group involves a top-down approach that tries to offer a definition for nonlinear polyphase systems in nonsinusoidal situations and apply it to linear single phase systems in sinusoidal situations by considering the former as the general case and the latter as a special case. This paper summarizes previously published approaches and concludes that none of the approaches in the literature can lead to power components definitions that satisfy all required power properties. Different analysis tools other than those based on frequency or time domain are recommended in this paper for future work. Index Terms--Nonsinusoidal conditions, power definitions, power theory, unbalanced systems.

The recent introduction and advancements in design of simple, constant-force mechanisms have created the potential for small-scale, low-cost, constant-force electronic connectors (CFECs). CFECs differ from traditional connectors by the separation or disassociation of contact normal force and contact deflection. By removing the traditional constraints imposed by forces and deflections that are dependent on each other, new types of electronic connectors can be explored. These new designs may lead to smaller and more reliable electronic connectors. In this paper, constant-force mechanisms are adapted to satisfy current industry practices for the design of electronic connectors. Different CFEC configurations are explored and one is selected, prototyped, and used as a proof-of-concept connector for a personal digital assistant (PDA) docking station. The modeling, optimization, and verification of the prototype CFEC is presented. Adaptation of constant-force technology to electronic connectors creates new possibilities in electronic connector designs, including allowing an optimal contact force to be utilized to decrease the effects of fretting and wear, lowering required manufacturing tolerances, reducing the system's sensitivity to variations introduced by the user, and increasing the system's robustness in applications where movement or vibrations exist. [DOI: 10.1115/1.2721080]

The application of power gating to cell-based semicustom design typically calls for customized cell libraries, which incurs substantial engineering efforts. In this brief, a semicustom design methodology for power gated circuits that allows unmodified conventional standard-cell elements is proposed. In particular, a new power network architecture is proposed for cell-based power gating circuits. The impact of body bias on current switch design and the layout method of current switch for flexible placement are investigated. The circuit elements that supplement cell-based power gating design are then discussed, including output interface circuits and state retention flip-flops. The proposed methodology is applied to ISCAS benchmark circuits and to a commercial Viterbi decoder with 0.18-[micro]m CMOS technology. Index Terms--Leakage, low power, power gating, semicustom, standard cell.

This paper proposes a bridgeless-type ac-side continuous-conduction-mode (CCM) current-source (CS) charge-pump (CP) power-factor-correction (PFC) electronic ballast. The drawbacks of conventional dc-side discontinuous-conduction-mode (DCM) electronic ballasts include high di/dt, high current stress, and high switching losses. As a result, conventional dc-side DCM CS-CP-PFC electronic ballasts have low efficiency, due to the DCM operation, and the ballasts require a large input electromagnetic interference filter. Conventional dc-side CCM CS-CP-PFC electronic ballasts are able to solve these problems, but still require a higher component count. To efficiently reduce the cost of electronic components, a bridgeless-type ac-side CCM CS-CP-PFC electronic ballast is proposed. A 32-W rated power electronic ballast prototype circuit is designed and implemented. Experimental results verify that the input-current harmonics meet the IEC 61000-3-2 Class-C Standard, and the CP capacitor helps the PFC inductor current to achieve CCM and high power factor. Index Terms--Charge-pump (CP), continuous-conduction-mode (CCM), current-source (CS), discontinuous-conduction-mode (DCM), electromagnetic interference (EMI), power-factor-correction (PFC).

Direct aluminum bonded (DAB) substrates have been developed. They can serve as isolating carriers especially for power electronic circuits or integrated components, respectively, using the standard assembly processes also applied to state of the art direct copper bonded (DCB) substrates. This new type of substrates has been characterized theoretically based on material properties of its layers and experimentally. While it behaves similar to DCB in many respects, the remarkably higher temperature cycling capability of DAB substrates constitutes a major difference, which is also useful to increase reliability of components exposed to extreme environmental temperatures. DAB based moulded integrated components with large chips in this respect have shown to reach a level of reliability which could not be achieved earlier with conventional technology. Outperforming the latter and complementing DCB, DAB can thus, in the future, be expected to explore new, and contribute to optimization of, existing applications with special demand for high reliability or also low weight. This makes this material well suited for use, e.g., in automotive power converters or avionic electronics. Index Terms--Ceramic insulators, direct aluminum bonded (DAB) substrates, direct copper bonded (DCB) substrates, power semiconductor devices, reliability.

We present a fully integrated differential distributed voltage-controlled oscillator implemented in a 0.35-[micro]m SiGe BiCMOS technology. The delay variation by a positive feedback tuning technique, adopted from the ring oscillators, is demonstrated as a fine-tuning alternative, which results to an approximately 420-MHz tuning range. The phase noise is -98 dBc/Hz at 1-MHz offset from the 14.25-GHz carrier. An integrated output buffer isolates the oscillator from the measurement equipment. The measured output power is -17.5 dBm and the overall power consumption of the chip is 138.1 mW employing two power supplies of 3.2 and 4.2 V, respectively. Index Terms--Distributed circuits, distributed oscillators, frequency tuning, output buffer, SiGe BiCMOS integrated circuits, transmission lines, voltage-controlled oscillators (VCOs).

In the design of printed circuit boards (PCBs), it is preferable to increase their fundamental frequency so as to reduce the effects of the dynamic loading on them. The dynamic characteristics of a PCB carrying various electronic components and modules are most significantly affected by the geometrical and material properties of the bare board and by the boundary conditions supporting the loaded PCB. In this research, a PCB carrying a heavy CPU cooling fan and supported by six fastening screws is investigated by the modal testing and analyzed by the finite element method. After the finite element model of the PCB is verified by the experimental results, the locations of the six supporting screws are optimized to achieve a maximum fundamental frequency for the loaded PCB. The position of each fastening screw can be determined by two design variables, i.e., x and y coordinates. Two cases are studied: the symmetric case (six design parameters) with the symmetric constraint on the support locations imposed, and the asymmetric case (12 design parameters) without the constraint imposed. Finally, verification experiments are performed on the two PCBs supported by screws located at the optimal positions. Although relatively large differences between the calculated, optimized fundamental frequencies and the experimental values are observed, the experiments confirm a very significant improvement in frequency for both cases. [DOI: 10.1115/1.2353281] Keywords: printed circuit boards (PCB), optimal support locations, maximum fundamental frequency, modal testing

The effects of altitude, increased ambient temperature, and increased relative humidity on the board level forced convection typical of telecommunications products were systematically examined through numerical simulation and analytical techniques. Altitude was found to have the most significant impact on component temperature rise above inlet air temperature. Depending on the proportion of upstream-heating to self-heating for a given component, the component temperature rise above inlet air temperature was found to increase by 40% to 88% at 5000 m when compared to the base line case at sea level. Inlet air temperature was found to translate linearly to component temperature increase. The second-order effects due to property changes with temperature were found to be less than 3% on the component temperature rise. The relative humidity was not found to significantly impact the component temperature rise at an inlet temperature of 25[degrees]C. However, the property changes at a 55[degrees]C inlet were more significant, and require further study. A temperature multiplier concept is introduced to aid practicing engineers in extrapolating data at standard conditions to the operating extremes.

The present paper determines numerically the optimal geometric parameters for the maximal peripheral cooling of a two-dimensional rectangular solid body with internal heat generation. The objective is to maximize the thermal global conductance (i.e., minimize the hot spot temperature on the solid body) by using the minimal cooling space. The flow is conducted around the heated solid body by a sequence of channels of independent width [D.sub.i], where 1 [less than or equal to] i [less than or equal to] 4. Each configuration is free to morph itself in two directions: (a) the number of cooling channels, and (b) the aspect ratio of the heated body [lambda]. The numerical results show that a number of cooling channels greater than one (i.e., n > 1) is profitable in terms of thermal performance when the heated body resembles a square (i.e., [lambda] ~ 1). However when [lambda] is free to vary, the thermal performance does not necessarily increase with the number of cooling channels. The paper also discusses the importance to allow each configuration to morph itself in multiple directions by comparing the thermal performance of similar configurations with different number of degrees of freedom. Scale analysis is used to verify the results obtained numerically for all the degrees of freedom considered. The numerical results agree with the scaling trends. [DOI: 10.1115/1.2351909] Keywords: electronic cooling, forced convection, heat transfer density, packing, compactness, constructal design

Thermal issues have become a major consideration in the design and development of electronic components. In power electronics, thermal limitations have been identified as a barrier to future developments such as three-dimensional integration. This paper proposes internal embedded cooling of high-density integrated power electronic modules that consist of materials with low thermal conductivity and evaluates it in terms of dimensional, material property, and thermal interfacial resistance ranges. Enhanced component conductivity was identified as a possible economically viable internal cooling option. Thermal performance calculations were performed numerically for conductive cooling of internal component/module regions via parallel-running embedded solids. Thermal advantage per volume usage by the embedded solids was furthermore optimized in terms of a wide range of geometric, material, and thermal parameters. In the dimensional and material property range commonly found in passive power electronic modules, parallel-running cooling layers were identified as an efficient cooling configuration. Numerically based thermal performance models were subsequently developed for parallel-running cooling inserts. A multifunctional experimental setup was constructed to study the cooling of ferrite (operated as a magnetic core) by means of embedded aluminium nitride layers and to verify the thermal model. Results corresponded well with theoretically anticipated performance increases. However, interfacial thermal resistance constituted a major limitation to the cooling performance and future power density increases. With the thermal model developed, functional optimization in terms of magnetic flux density for parallel-running cooling layer configurations was performed for a wide range of material and geometric conditions. [DOI: 10.1115/1.2351903]

This paper presents an analysis of an unexpected failure during vibration and shock life test of an electronic circuit board that has been in use for more than 15 years. During testing, an aluminum bracket used to mount a transistor and provide a path for heat transfer was damaged. Prognostic methods were employed to determine whether the bracket failure could have been predicted prior to the life test. Details of the analytical calculations and modeling results are described in this paper. Results show that the failure could have been predicted before actual testing. [DOI: 10.1115/1.2351897]

Microprocessor technology, broader bandwidth communications, and cheaper storage medium have greatly improved the capability to process, transmit, and store the large quantities of data available in a substation. Intelligent electronic devices (IEDs) normally acquire some of these data as raw facts, which then need to be interpreted in order to extract the useful information that engineers and operators require. Human interpretation is becoming increasingly impractical and the effect can hamper, or even prevent, an operator responding correctly to an emergency. This paper explains how a rough classification technique enhances the capabilities of substation informatics and provides valuable insight into the information contained in a substation dataset. This paper emphasizes postfault analysis of the protection and breaker responses in a substation. It is designed to help the operator understand overwhelming alarm messages or longer term to help engineers analyze what went wrong. The formulated methodology is generic and applicable to any type of transmission and distribution substation. Index Terms--Discernibility matrix, intelligent electronic devices (IEDs), knowledge extraction, rough sets, unsupervised event extraction.

In digital hardware system design, the quality of the product is directly related to the number of meaningful design alternatives properly considered. Unfortunately, existing modeling methodologies and tools have properties which make them less than ideal for rapid and accurate design-space exploration. This article identifies and evaluates the shortcomings of existing methods to motivate the Liberty Simulation Environment (LSE). LSE is a high-level modeling tool engineered to address these limitations, allowing for the rapid construction of accurate high-level simulation models. LSE simplifies model specification with low-overhead component-based reuse techniques and an abstraction for timing control. As part of a detailed description of LSE, this article presents these features, their impact on model specification effort, their implementation, and optimizations created to mitigate their otherwise deleterious impact on simulator execution performance. Categories and Subject Descriptors: 1.6.2 [Simulation and Modeling]: Simulation Languages; I.6.5 [Simulation and Modeling]: Model Development--Modeling methodologies; C.4 [Performance of Systems]--Modeling techniques; I.6.7 [Simulation and Modeling]: Simulation Support Systems--Environments General Terms: Design, Experimentation, Human Factors, Languages Additional Key Words and Phrases: Liberty Simulation Environment (LSE), structural modeling, simulator construction, component reuse

One of the most attractive features of MOBILE-based circuits is their self-latching operation, which allows pipelining at the gate level, and thus very high through-output, without any area overhead associated to the addition of the latches. However, the self-latching behavior is not inherent to the practical circuit topologies employed to implement MOBILE circuits. This paper reports on very simple MOBILE structures supporting this statement. The analysis performed is useful in extracting design guidelines to guarantee the required behavior. Index Terms--MOBILE, resonant tunnel diode, self-latching.

Three-dimensional (3-D) integrated circuits (ICs), with multiple stacked device layers, offer a unique design opportunity to use both bulk and partially depleted (PD) silicon-on-insulator (SOI) CMOS devices in a single circuit design. Such 3-D designs can, for example, minimize the body effect common in bulk designs and reduce adverse floating-body effects (FBE) common in PD SOI designs. Sequential 3-D technology such as exfoliation-based single-crystal silicon layer transfer allows a low-temperature approach to 3-D integration with high-density interconnectivity. Using the characteristics of this technology, we present the mixed SOI bulk (MSB) design approach that effectively re-maps conventional VLSI designs to the 3-D design space. Tradeoffs in delay, noise margin, power, and circuit footprint are analyzed and demonstrated through analyzes of static, dynamic, pass-transistor, and SRAM circuits. Index Terms--Circuit optimization, integrated circuit (IC) technology, silicon-on-insulator (SOI) technology, three-dimensional (3-D) ICs, 3-D integration, 3-D SRAM.

This paper presents the related principle and analysis of the dimmable electronic ballast controlled by the switch-controlled capacitor (SCC). A Fourier-series expansion is used to derive the operational principle of the zero-voltage-switching Class-D series-parallel-load-resonant dimmable electronic ballast regulated by the SCC. By the adaptation of the SCC, the lightness of the system can be adjusted, while the operation frequency of the Class-D converter can be kept constant. The dimmable effect controlled by the variable SCC is examined. The analytical results are verified by simulations and experiments. Furthermore, the design considerations for the dimmable electronic ballast with SCC control are also presented in this paper. Index Terms--Dimmable electronic ballast, Fourier-series expansion, phase-shift c~, switch-controlled capacitor (SCC).

A modified transconductance amplifier with low harmonic distortion and high current efficiency is proposed. It can be used in high-frequency applications up to 10 MHz. Each half of the transconductor differential input stage consists of a pair of transistors in saturation and linear regimes with a voltage feedback loop. Results of theoretical analysis are confirmed by SPICE simulations. Index Terms--Feedback, harmonic distortion, noise, transconductance amplifier, transconductor.

A multistandard/multiband adaptive voltage-controlled oscillator (VCO) satisfying the phase-noise requirements of both second- and third-generation wireless standards is described in this paper (1.8-GHz DCS1800, 2.1-GHz wide-band code division multiple access, and 2.4-GHz wireless local area network, Bluetooth, and digital enhanced cordless telecommunications standards). The design procedure for the VCO is based on an adaptive phase-noise model. A factor of 12 reduction in power consumption with a phase-noise tuning range of 20 dB is demonstrated by adapting the VCO bias to the desired application. The VCO achieves -123-, -110-, and -103-dBc/Hz phase noise at 1-MHz offset in a 2.1-GHz band at supply currents of 6, 1.2, and 0.5 mA, respectively. Index Terms--Adaptive circuits, loop gain, multistandard (MS)/multiband (MB) circuits, phase noise, phase-noise tuning, voltage-controlled oscillators (VCOs).