84 results on '"Ciofi, I."'
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2. Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node
3. Semi-damascene Integration of a 2-layer MOL VHV Scaling Booster to Enable 4-track Standard Cells
4. Reliability benchmark of various via prefill metals
5. Reliability Evaluation of Semi-damascene Ru/Air-Gap interconnect with Metal Pitch down to 18 nm
6. A new methodology for modeling Air-Gap TDDB
7. Line-to-Line TDDB Modeling: LER Specs for Sub-20-nm Pitch Interconnects
8. Evaluating k-values for low -k materials after damascene integration: Method and results
9. Assessment of critical Co electromigration parameters
10. Process Integration of High Aspect Ratio Vias with a Comparison between Co and Ru Metallizations
11. Correlation between trench depth and TDDB thermal activation energy in single damascene Cu/SiOC:H
12. Supervia Process Integration and Reliability Compared to Stacked Vias Using Barrierless Ruthenium
13. Inflection points in interconnect research and trends for 2nm and beyond in order to solve the RC bottleneck
14. The reliability margin of interconnects for advanced memory technologies
15. Ultra Low-k Materials Based on Self-Assembled Organic Polymers
16. Correlation between stress-induced leakage current and dielectric degradation in ultra-porous SiOCH low-k materials.
17. Towards understanding intrinsic degradation and breakdown mechanisms in SiOCH low-k dielectrics.
18. Three-Layer BEOL Process Integration with Supervia and Self-Aligned-Block Options for the 3 nm Node
19. Electromigration scaling limits of copper interconnects
20. Impact of material/process interactions on the properties of a porous CVD-O 3 low-k dielectric film
21. Interconnect metals beyond copper: reliability challenges and opportunities
22. Damascene Benchmark of Ru, Co and Cu in Scaled Dimensions
23. System-Level Impact of Interconnect Line-Edge Roughness
24. Testing The Limits of TaN Barrier Scaling
25. Insights into metal drift induced failure in MOL and BEOL
26. Method to assess the impact of LER and spacing variation on BEOL dielectric reliability using 2D-field simulations for <20nm spacing
27. Single exposure EUV patterning of BEOL metal layers on the IMEC iN7 platform
28. On-chip interconnect trends, challenges and solutions: How to keep RC and reliability under control
29. Modeling of graphene for interconnect applications
30. Semi-empirical interconnect resistance model for advanced technology nodes: A model apt for materials selection based upon test line resistance measurements
31. Correlation between stress-induced leakage current and dielectric degradation in ultra-porous SiOCH low-k materials
32. Vertical device architecture for 5nm and beyond: Device & circuit implications
33. Intrinsic reliability of local interconnects for N7 and beyond
34. Impact of process variability on BEOL TDDB lifetime model assessment
35. Towards understanding intrinsic degradation and breakdown mechanisms in SiOCH low-k dielectrics
36. Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies
37. Towards the understanding of intrinsic degradation and breakdown mechanisms of a SiOCH low-k dielectric
38. Cu Wire resistance improvement using Mn-based Self-Formed Barriers
39. Temperature Controlled Oven for low noise measurements systems
40. Correlation between field dependent electrical conduction and dielectric breakdown in a SiCOH based low-k (k = 2.0) dielectric
41. Methodology for extracting the characteristic capacitances of a power MOSFET transistor, using conventional on-wafer testing techniques
42. Integration of a k=2.3 spin-on polymer for the sub-28nm technology node using EUV lithography
43. Impact of LER on BEOL dielectric reliability: A quantitative model and experimental validation
44. Low-k dielectric reliability: impact of test structure choice, copper and integrated dielectric quality
45. Cu Resistivity Scaling Limits for 20nm Copper Damascene Lines
46. Reliability challenges for advanced copper low-k interconnects
47. Moisture Related Low-K Dielectric Reliability Before and After Thermal Annealing.
48. Impact of material/process interactions on the properties of a porous CVD-O3 low-k dielectric film
49. Temperature controlled oven for low noise measurement systems [for electromigration characterization]
50. Integration of 20nm half pitch single damascene copper trenches by spacer-defined double patterning (SDDP) on metal hard mask (MHM).
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