427 results on '"Chung-Len Lee"'
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2. A novel test scheme for NAND flash memory based on built-in oscillator ring.
3. Enhanced error correction against multiple-bit-upset based on BCH code for SRAM.
4. A folded current-reused CMOS power amplifier for low-voltage 3.0-5.0 GHz UWB applications.
5. A test pattern selection method for dynamic burn-in of logic circuits based on ATPG technique.
6. A UWB mixer with a balanced wide band active balun using crossing centertaped inductor.
7. Modeling and testing of interference faults in the nano NAND Flash memory.
8. A reconfigurable MAC architecture implemented with mixed-Vt standard cell library.
9. Arbitrary Waveform Generator Based on Direct Digital Frequency Synthesizer.
10. A Fast Two-Stage Sample-and-Hold Amplifier for Pipelined ADC Application.
11. A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs.
12. IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults.
13. Oscillation ring based interconnect test scheme for SOC.
14. Finite State Machine Synthesis for At-Speed Oscillation Testability.
15. Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle.
16. Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing.
17. A Scan Matrix Design for Low Power Scan-Based Test.
18. Multilevel full-chip routing with testability and yield enhancement.
19. A New Path Delay Test Scheme Based on Path Delay Inertia.
20. A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DAC.
21. A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI.
22. An On-Chip Jitter Measurement Circuit for the PLL.
23. A Low Power High Speed Class-B Buffer Amplifier for Flat Panel Display Application.
24. A Testing Scheme for Crosstalk Faults Based on the Oscillation Test Signal.
25. A computer aided engineering system for memory BIST.
26. Socillator Test: A Delay Test Scheme for Embedded ICs in the Boundary-Scan Environment.
27. A methodology for fault model development for hierarchical linear systems.
28. Is IDDQ testing not applicable for deep submicron VLSI in year 2011?
29. Fault diagnosis for linear analog circuits.
30. All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses.
31. A DFT for semi-DC fault diagnosis for switched-capacitor circuits.
32. An Effective Methodology for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits.
33. Analog Metrology and Stimulus Selection in a Noisy Environment.
34. Maximization of power dissipation under random excitation for burn-in testing.
35. Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation.
36. Functional test pattern generation for CMOS operational amplifier.
37. Invalid State Identification for Sequential Circuit Test Generation.
38. Factorization of Multi-Valued Logic Functions.
39. On Designing of 4-Valued Memory with Double-Gate TFT.
40. Fanout fault analysis for digital logic circuits.
41. A programmable multiple-sequence generator for BIST applications.
42. TRANS: A Fast and Memory-Efficient Path Delay Fault Simulator.
43. Algebraic Division for Multilevel Logic Synthesis of Multi-Valued Logic Circuits.
44. Synthesis of Multi-Variable MVL Funtions Using Hybrid Mode CMOS Logic.
45. Complete Test Set for Multiple-Valued Logic Networks.
46. SEESIM - a fast synchronous sequential circuit fault simulator with single event equivalence.
47. Fault Analysis on Two-Level (K+1)-Valued Logic Circuits.
48. A Probabilistic Testability Measure for Delay Faults.
49. Single-fault fault collapsing analysis in sequential logic circuits.
50. A Parallel Pattern Mixed-Level Fault Simulator.
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