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Abstract Epidermal sensors for remote healthcare and performance monitoring require the ability to operate under the effects of bodily motion, heat, and perspiration. Here, the use of purpose‐synthesized polymer‐based dry electrodes and graphene‐based strain gauges to obtain measurements of swallowed volume under typical conditions of exercise is evaluated. The electrodes, composed of the common conductive polymer poly(3,4 ethylenedioxythiophene) (PEDOT) electrostatically bound to poly(styrenesulfonate)‐b‐poly(poly(ethylene glycol) methyl ether acrylate) (PSS‐b‐PPEGMEA), collect surface electromyography (sEMG) signals on the submental muscle group, under the chin. Simultaneously, the deformation of the surface of the skin is measured using strain gauges comprising single‐layer graphene supporting subcontinuous coverage of gold and a highly plasticized composite containing PEDOT:PSS. Together, these materials permit high stretchability, high resolution, and resistance to sweat. A custom printed circuit board (PCB) allows this multicomponent system to acquire strain and sEMG data wirelessly. This sensor platform is tested on the swallowing activity of a cohort of 10 subjects while walking or cycling on a stationary bike. Using a machine learning (ML) model, it is possible to predict swallowed volume with absolute errors of 36% for walking and 43% for cycling.

Continued scaling in accordance with Moore’s law is becoming increasingly difficult. Pitch shrinkage and standard cell height reduction via design technology co-optimization with design rules have sustained this scaling until recently. However, we observe that standard cell device scaling is becoming saturated due to yield and cost. One way to continue device footprint reduction is by expanding in the third dimension via monolithic 3D integration, using for example stacked gate-all-around (GAA) devices, complementary FETs, vertical FETs, and 3D logic. However, using these footprint scaling approaches to increase device density creates new problems. Using vertical gate-all-around FET (VFET) technologies as a specific instance of 3D device scaling, we demonstrate that the key bottleneck to footprint scaling is the pin density wall. The footprint of a block is predominantly limited by the pin density as we increase the number of active device layers. While a full-blown paradigm shift on layout methodology, design flow, and electronic design automation (EDA) platform is not available now, we describe in this article three specific baby steps that can alleviate the pin density problem and demonstrate their potential benefits for footprint scaling: (1) allocating standard cell pin sideways and using block-level routing with the local interconnect layers; (2) using the backside of the substrate for the power distribution network; and (3) using the generation of more complex standard cells. We show via several core designs that a 42.6% reduction in the core area is achievable when a combination of these operations is employed.

With the relentless scaling of technology nodes, the track number reduction of conventional (Conv.) cell is starting to reach its limitations due to limited routing resources, lateral p-n separations, and performance requirements. As a result, to exploit the benefits of 3-D architectures, complementary-FET (CFET) technology, which stacks P-FET on N-FET or vice versa, is proposed to release the restriction of p-n separation and reduce in-cell routing congestion by enabling p-n direct connections. However, CFET standard cell (SDC) synthesis demands a holistic reconsideration of multirow (MR) structure to maximize the cell and block-level area benefits due to limited in-cell routing tracks and routability that comes from the stacked structure and reduced cell height. In this article, we propose a satisfiability modulo theory (SMT)-based MR CFET SDC synthesis framework that simultaneously solves place-and-route to minimize the cell area by considering single-row and MR placement together. We enable explorations on upper/lower M0A/PC routing to leverage the shared-and-split structure across cell rows with the proposed MR dynamic complementary pin allocation scheme. We demonstrate that MR 2.5T CFET without and with upper/lower M0A/PC routing achieves 16.44% and 20.61% on the average reduced cell areas, respectively, compared to 3.5T CFET. Moreover, MR 2.5T CFET SDCs achieve 13.43% and 14.40% less block-level area and total wirelength on average compared to 3.5T CFET SDCs.

Many-tier vertical gate-all-around nanowire FET (VFET) synthesis strongly demands a holistic approach of modeling/formulating/optimizing transistor placement and in-cell routing to obtain the maximum-achievable power, performance, area, and cost (PPAC) benefits. In this article, we propose a novel satisfiability modulo theories (SMT)-based many-tier VFET standard cell (SDC) synthesis framework that simultaneously solves place-and-route (P&R). We devise an extended relative positioning constraint and a dummy gate control scheme to capture the unique VFET cell architecture. Moreover, we present efficient objectives to improve pin-accessibility and reduce the use of vertical routing, which has high resistance. Compared to the conventional sequential P&R approach, our concurrent P&R achieves a 15.2% smaller cell area on average for 2-tier VFET. Throughout the extensive exploration for many-tier VFET configurations up to 4-tier, we show that the 4-tier VFET respectively achieves 50.1% and 27.9% of average area reduction on chip-level and block-level, over 4.5T GAAFET.

Blast-related mild traumatic brain injury (bmTBI) often leads to long-term sequalae, but diagnostic approaches are lacking due to insufficient knowledge about the predominant pathophysiology. This study aimed to build a diagnostic model for future verification by applying machine-learning based support vector machine (SVM) modeling to diffusion tensor imaging (DTI) datasets to elucidate white-matter features that distinguish bmTBI from healthy controls (HC). Twenty subacute/chronic bmTBI and 19 HC combat-deployed personnel underwent DTI. Clinically relevant features for modeling were selected using tract-based analyses that identified group differences throughout white-matter tracts in five DTI metrics to elucidate the pathogenesis of injury. These features were then analyzed using SVM modeling with cross validation. Tract-based analyses revealed abnormally decreased radial diffusivity (RD), increased fractional anisotropy (FA) and axial/radial diffusivity ratio (AD/RD) in the bmTBI group, mostly in anterior tracts (29 features). SVM models showed that FA of the anterior/superior corona radiata and AD/RD of the corpus callosum and anterior limbs of the internal capsule (5 features) best distinguished bmTBI from HCs with 89% accuracy. This is the first application of SVM to identify prominent features of bmTBI solely based on DTI metrics in well-defined tracts, which if successfully validated could promote targeted treatment interventions.