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In this study, adding CsPbI3 quantum dots to organic perovskite methylamine lead triiodide (CH3NH3PbI3) to form a doped perovskite film filmed by different temperatures was found to effectively reduce the formation of unsaturated metal Pb. Doping a small amount of CsPbI3 quantum dots could enhance thermal stability and improve surface defects. The electron mobility of the doped film was 2.5 times higher than the pristine film. This was a major breakthrough for inorganic quantum dot doped organic perovskite thin films.

In this paper, the effect of channel annealing and oxygen flow rate in P-type tin-monoxide (SnO) thin film transistor (TFT) was investigated to reach the process compatibility with n-type oxide-based TFT. The optimized P-type SnO TFT with a small threshold voltage of -0.1 V, a high field-effect mobility of 4 cm² V-1 s-1 and an on/off current ratio of >10² was proposed. From the experimental results, the 150 °C channel annealing revealed a metallic behavior but a semiconductor-like property at a higher 200 °C that was favorable for transistor rectification. Besides, the higher oxygen flow rate was also helpful for improving device mobility and driving current, but shows a slight increase in off-state leakage, which is unavoidable due to the increase of grain in SnO channel.

The layout effect influences the performance of nanoscale devices with advanced strain engineering, considering that the size of a technology node continuously shrinks to ≤ 20 nm. Transistors with a long gate width could be fabricated, and the portion that protrudes outside the channel region could be located on a soft shallow trench isolation region and even across the dummy active region of diffusion. Induced strained silicon technology should be considered when managing and enhancing mobility gain in devices with narrow channel widths. Thus, we fabricated a 20 nm silicon-based n-type metal-oxide-semiconductor field-effect transistor with a Si0.75Ge0.25 alloy channel and a + 3.0 GPa tensile contact etch stop layer as stressors. The transistor was utilized at different dummy gate arrays and dummy poly pitches. The fabricated device was subjected to oriented stress simulation, and the relationship between the piezoresistance effect and the stress component within the device channel was investigated. The best performance, which was 40% higher than that of conventional transistors, was observed in the transistor with 100 nm gate width.

In recent years, the study of organic–inorganic halide perovskite as an optoelectronics material has been a significant line of research, and the power conversion efficiency of solar cells based on these materials has reached 25.5%. However, defects on the surface of the film are still a problem to be solved, and oxygen plasma is one of the ways to passivate surface defects. In order to avoid destroying the methylammonium lead iodide (MAPbI3), the influence of plasma powers on film was investigated and the cesium triiodide (CsPbI3) quantum dots (QDs) were doped into the film. In addition, it was found that oxygen plasma can enhance the mobility and carrier concentration of the MAPbI3 film.

In this paper, we have demonstrated an oxygen-vacancy-based bipolar RRAM on a pure logic 14-nm-node HKMG FinFET platform. A unit cell of the memory consists of a control transistor (FinFET) and a storage transistor (a second FinFET). The later performs as a bipolar RRAM. This unit cell can be integrated in an AND-type memory array. The memory cell has an ON/OFF ratio equal to 200 and 400 for the n-type and p-type FinFET RRAMs, respectively, endurance larger than 400 and 1000 times for n- and p-type devices, respectively, and the retention test for over 1 month under 125 °C temperature environment. To analyze the array performance of the AND-type FinFET RRAM at the circuit level, we have further discussed the issues of the sneak path and disturbance, in which an active-fin isolation of FinFET in an AND-type array has been suggested to minimize the leakage current induced by sneak paths. The results have shown a large window with up to 103 ON/OFF ratio, 30% standby power reduction, and 90% active power reduction with reference to the conventional AND-type array. As a result, the bipolar FinFET RRAM exhibits great potential for the embedded memory applications, in particular it can be extended to 28-nm HKMG and the FinFET platform beyond 14-nm technology node, to fill the Moore’s gap between the high-performance logic and the embedded memory.

The intrinsic stress of thin films has become an important resource as advanced strain engineering is introduced into nanoscaled semiconductor devices. The performance of preferred device infrastructure can be studied by estimating stress-induced mobility gain. However, traditional simulation approaches for device stress typically do not consider the eventual consequence of the stress gradient of strained thin films on nanoscaled transistor stress prediction. Thus, the actual operating characteristic of concerned devices can be easily misunderstood. To resolve this issue, this research presents a fabrication-oriented simulation methodology for device stress and combines it with a multi-layered deposition model for thin film. This study aims to explore stress-induced effects on the performance of a Ge-based testing vehicle for 20 nm n-type metal-oxide-semiconductor field-effect transistors (nMOSFETs) with Ge 1−x Si x alloys embedded into the source/drain regions of the device. Intrinsic stress is introduced via a 1.0 GPa tensile contact etch stop layer (CESL). Analysis results indicate that stress contours adjacent to the top of the device gate are different from those obtained using the conventional simulation method. Moreover, greater CESL stress passes through the spacer and reaches the device channel. Furthermore, a relationship between the stress components and piezoresistivity coefficients of the Ge material is adopted to estimate the width dependence of the Ge-based nMOSFET on its mobility gain. A maximum mobility gain of up to 60.87% is acquired from the estimated results, and a channel width of 200 nm is preserved.

In this work, a novel concept of 2-bit-per-cell (2B/C) is introduced to realize high-density OTP PUF from a new scheme of dielectric breakdown. This PUF shows $10^{5}{\text{x}}$ of large window, good immunity to high-temperature disturbance, and excellent retention under 150°C baking, which are particularly for automotive applications. In terms of security, this PUF exhibits near ideal normal distribution of hamming distance and narrow distribution of hamming weight. The bit error rates are low, 0.78% at 25°C and 1.95% at 150°C, benchmarked on a 256-bit array. Finally, the security test of this PUF against the hackers' attack from the machine learning process has been proved to have high security. Overall, the proposed 2B/C OTP PUF demonstrated great potential for IoT security in 5G era.

We develop experimental approaches to quantitatively extract the negative capacitance of MIM in a gate stacked NCFET. It was found that the NC effect is highly dependent on the grain and dipole behaviors with different annealing temperature. Also, to achieve a better design of high-performance NCFET, we explore not only the capacitance matching between ferroelectric HZO MIM and MOSFET but also how effective mobility is affected by HZO dipoles. For capacitance matching, we observe a 50x enhancement of overall gate capacitance triggered by NC effect, while, however, it adversely generated the degradation of the mobility. This mobility degradation is induced by the remote scattering from the ferroelectric HZO dipoles. Fortunately, if suitable polarization can be formed to align the HZO dipoles, the effects of remote scattering can be mitigated. From a trade-off between gate capacitance and the mobility, an NCFET with desirable performance can be achieved.

A novel concept of OTP has been demonstrated to create another feasibility to allow re-writable capability before storing the data. This OTP is named Rewritable One-time- programming (RW-OTP) memory. With RW-OTP, users can do the test by modifying the contexts repeatedly before finalizing the stored data. To implement the memory cell, it consists of a gate-floated FinFET and an RRAM where a bilayer has been designed as a thicker dielectric layer with resistive-switching property on a thinner dielectric-fuse layer. Moreover, the process of RW-OTP is fully compatible with the state-of- the-art CMOS logic technology. The result shows that the memory cell exhibits high retention and good endurance. With proper use of RW-OTP, the users can not only reduce error jobs cost-efficiently but also can develop various applications for their needs. This memory cell is very promising for embedded applications.

This study was conducted by integrating Atayal culture into CPS education strategy to develop spatial concept courses, teaching materials, and assessment tests that served to analyze the effectiveness of spatial concept learning on indigenous students after two years of course. The participants of this study were 16 5th grade students from an Atayal elementary school located in Nan’ao, Yilan County. The period of study spanned from 2015 to 2016, and was conducted by gathering data through teaching demonstrations and tests. The tests developed for this study were used as the research tool, and had been examined and pretested by 3 content specialists. The finalized tests included a total of 19 segments (59 problems) on 6 spatial concepts: “rotation”, “reflection”, “folding”, “perspective”, “stacking”, and “cubic enumeration”. The tests were conducted before and after the study and verified against sample t to examine if the indigenous students’ spatial concepts exhibited significant changes. Study results showed that with regard to the 6 different spatial concept tests, indigenous students performed significantly better in the after-tests than in the pre-tests. The integration of Atayal culture into CPS spatial concept courses was therefore determined to have significant positive impact on the spatial concepts of indigenous students.

In this study, a Y 2 O 3 film doped with Zr was fabricated to form two stacked structures, Al/ZrN/Y 2 O 3 + Zr/Y 2 O 3 /p-Si (with Zr in the upper layer) and Al/ZrN/Y 2 O 3 /Y 2 O 3 + Zr/p-Si (with Zr in the lower layer), at rapid thermal annealing (RTA) temperature range of 550, 700, and 850 °C. To analyze the leakage current mechanism, leakage current versus voltage (I–V) and capacitance versus voltage (C–V) characteristics of these two structures were first investigated. By analyzing Schottky emission (SE) and the fit of its equation with experimental data and parameters, dielectric constants were computed to be 11.3 and 6.34, equivalent oxide thicknesses (EOTs) were determined to be 2.42 and 4.3 nm, Schottky barrier heights were calculated to be 0.81 and 0.82 eV, and dynamic dielectric constants were determined to be 13 and 8 for structures with Zr in the upper and lower layers, respectively. By analyzing Poole–Frenkel (P–F) emission and the fit of its equation with experimental data and parameters, trap energy levels were computed to be 0.45 and 0.5 eV, and dynamic dielectric constants were determined to be 1.65 and 2.61 for structures with Zr in the upper and lower layers, respectively. The characteristics of ln( J / T 2 ) versus E 0.5 and ln( J / T 2 ) versus 1000 T in SE and P–F emission were linear, thus conforming to the theoretical equations. Finally, the results of computed parameters in the two structures were compared to validate the leakage current mechanism.

Decoupled plasma nitridation (DPN) or post-deposition annealing (PDA) process after high-k (HK) deposition to repair the bulk traps or the oxygen vacancy in gate dielectric is an impressive choice to raise up the device performance. Before heat stress, the electrical performance in drive current, channel mobility and subthreshold swing with both treatments was approximate, except the higher annealing atmosphere causing the thicker interfacial layer and reducing the overall related dielectric constant. After temperature stress, the electrical performance for all of the tested devices was slightly deteriorated. The degradation degree for electrical performance with PDA treatment group was the worst case due to NH3 atmosphere forming Si–H bond on the channel surface, which was broken after stress and produced more interface state reflected with the increase of subthreshold swing.

The stress induced by strain in the channel of metal oxide semiconductor field effect transistors (MOSFET) is an effective method to boost the device performance. The geometric dimensions of spacer, gate height, and the contact etch stop layer (CESL) are important factors among the feasible booster. This study utilized the mismatch of the thermal expansion coefficients of stressors to simulate the process-induced stress in the N-MOSFET. Different temperatures are applied to different region of the device to generate the required strain. The analysis was performed by well-developed finite element package. The composite spacers with variant width of inserted silicon nitride (SiO2/SiN/SiO2, ONO) were proposed and their impacts on channel stress were compared. Two aspects of the impacts of those factors on the channel stress in the longitudinal direction for N-MOSFET with variant channel length were investigated. Firstly, the channel stresses of device without CESL for different gate heights were studied. Secondly, with stress applied to CESL and ONO spacers, the induced stresses in the channel were analyzed for long/short gate length. Two conclusions were drawn from the results of simulation. The N-MOSFET device without CESL shows that the stressed spacer alone generates compressive stress and the magnitude increases along with higher gate height. The channel stress becomes tensile for device with CESL and increases when the thickness of CESL and the height of gate increase, especially for device with shorter gate length. The gate height plays more significant role in inducing channel stress compared with the thickness of CESL. The channel stress can be used to quantify the mobility of electron/hole for strained MOSFET device. Therefore, with the guideline disclosed in this study, better device performance can be expected for N-MOSFET.

In this research, an n-type metal-oxide-semiconductor field effect transistor (nMOSFET) device with a SiGe channel exerted by the combination of a contact etching stop layer (CESL) and silicon germanium (Si1-xGe(x)) channel stressors is proposed. To explore the foregoing mechanical effect on the stress distribution of nMOSFETs within the channel region, a process-oriented simulated technique is adopted for the concerned nMOSFET device. The loading sources are a 1.1 GPa tensile CESL (t-CESL) and a SiGe channel structure constructed with 0%, 22.5%, and 25%, germanium (Ge) mole fractions. The results of the simulation show that the stress components of the Si1-xGe(x) channel evidently increase when the Ge mole fraction within a Si1-xGe(x) layer is increased. A pulling force exerted on the protruding gate structure by the CESL layer that causes dominant bending deformation and channel stress variation behaviors is a major reason for this phenomenon. Therefore, the degree of bending effect caused by the protruding gate structure is concluded as being the key to determining the trends and stress magnitudes of the Si1-xGe(x) device channel.

As the strained engineering technology of metal-oxide-semiconductor field effect transistors (MOSFET) is scaled beyond the 22 nm node critical dimension, shallow trench isolation (STI) becomes one of the most important resolutions for isolate devices to enhance the carrier mobility of advanced transistors. Several key design factors of n-type MOSFET (NMOSFET) under the resultant loadings of STI structures and contact etching stop layers are sensitively analyzed for silicon channel stress via finite element method-based simulations integrated with the use of design of experienmnts. NMOSFETs with 15 nm deep sunken STI have achieved a ~5% mobility enhancement as compared with a regular STI shape. By adopting simulation-based factorial designs, we have determined that the design factor of recess depth in STI is a critical factor influencing device performance. Moreover, a response surface curve on carrier mobility of NMOSFET under a consideration of combining the sunken STI and source/drain lengths is further presented in this research.

Background:The main objective of this study was to investigate and compare the spatial conceptualization performance for sixth grade elementary school students from urban, suburban and remote schools in Taiwan.Material and methods:This study involved 27, 25, and 26 sixth grade students from one remote indigenous school in eastern Taiwan, one suburban indigenous school in northern Taiwan, and one urban Han Chinese school in northern Taiwan, respectively. Spatial ability assessments were carried out on the students to explore the spatial conceptualiza-tion abilities and the possible relationship between school children's spatial abilities and urban-rural, ethnic, and cultural diversities.Results:The research tool utilized in this study was a scenario-based spatial ability assessment test, which had been carefully reviewed and pre-tested by experts. Test results revealed that: (1) Sixth grade students from the sub-urban and remote indigenous school shared no significant difference in their spatial abilities; (2) Sixth grade students from the urban Han Chinese school exhibited significantly better spatial performance than those from the suburban indigenous school.Conclusions:The spatial conceptualization performance for sixth grade elementary school students from urban, suburban and remote schools in Taiwan is different.

For the first time, the ion-vacancy-based bipolar RRAM has been demonstrated on HKMG stack of FEOL logic 14nm FinFET. A unit cell with two identical FinFETs, one serves as a control transistor and the other one is the storage with resistance switching. It is performed by the edge tunneling and with bipolar switching. More importantly, the sneak path issue in an AND-type array based on this FinFET unit cell has been thoroughly investigated. To solve sneak path issue, a new active-fin-isolation (AFI) of FinFET in an AND-type array was proposed. This new AFI effectively increases the S/N margin of 103 and significantly reduces the standby power of 30% and active power of 99%, compared to original AND-type array. This work provides a promising candidate for the embedded FLASH memory on FinFET platform featuring fully-CMOS compatible integration and low cost solution in the more-than-Moore era.

This paper presents an augmented-reality based interaction gear game which is designed to be used as a learning material of Science and Technology course for elementary school students. With this game, the authors hope to increase concentration, interest, and efficiency of learning in class. Basically, through obtaining the coordinates of human skeleton with Kinect sensor, we are able to identify the user's physical movements and postures and design scenarios in the game; the virtual picture is shown in the image, and therefore, the user can interact with the picture in an audio-visual scenario. This game makes learning through interacting possible. It provides a learning course that educates and entertains. In addition, it helps students to learn the scientific concept of gear during the interaction.

A novel complementary tunneling FET (C-TFET) has been designed and targeted for the low power and appropriate performance applications (Apps). In this new architecture of C-TFET, the drain and source (D/S) are configured as a staggered structure to increase the tunneling current, and the conventional p-i-n junction C-TFET has been modified as a p-n junction to further enhance the I on current. The results show that new design can achieve 310uA/um(n), 440uA/um(p) TFETs of I on , comparable to those of LP planar CMOS devices, 0.1 nA/um of I off , while excellent S.S.(

A new theory has been developed for geometric variation of trigate FinFETs. This geometric variation includes both line roughness induced variation and oxide-thickness variation, which can be measured from gate capacitance and Ig current variations, respectively. Experimental results show that trigate devices are subject to serious line variations as the fin height scales up and the fin-width scales down, leading to large I on current variation, i.e., as we increase the fin aspect-ratio, line variation becomes worse which shows an increase of the active power consumption. On the other hand, oxide-thickness variation reveals significant impacts on the off-state leakage, i.e., a rough gate oxide yields to larger static power. These valuable results provide us important guideline for the design and manufacturing of high quality 3D gate FinFETs.

The mobility enhancement of metal-oxide-semiconductor field-effect transistors (MOSFETs) using narrow gate lengths and channel widths is sensitive to the stress effects of silicon channels related to advanced strain engineering. The layout pattern of MOSFETs significantly influences the device performance, particularly the protruding gate width on shallow trench isolation structures. This paper investigates the geometric construction of an n-channel MOSFET composed of silicon–carbon stressors embedded in source/drain regions. The stressors have a 1.65% carbon mole fraction and a 1.1 GPa tensile contact etch stop layer. Finite element analysis and analysis of variance were used to determine the bending effect of protruding gate widths on the MOSFETs. Results show that the main variation parameters are channel lengths and protruding gate widths, which determine the improvement in device performance. These results can serve as guidelines of stress impacts for predicting the next-generation node technologies of layout patterns.

The layout patterns of nano-scale devices have significant impacts on device performance when an increase in operating velocity is considered. Thus, advanced strain engineering of metal-oxide-semiconductor field-effect transistors (MOSFETs) is necessary when highly scaled gate lengths are employed. The foregoing mechanical effects are observable when a device with a narrow channel width is utilized. However, when a device integrated with an extended poly gate is scaled down to several hundreds of nanometers, the induced stress contours of the channel region and corresponding mobility gain become troublesome and must be resolved. This study investigates the mechanical impacts of extended gate widths on the mobility gains of p-type MOSFETs. The selected MOSFET has a SiGe stressor embedded in its source and drain regions, as well as a compressive contact etch stop layer. Three-dimensional finite element simulation is performed to emulate the stress contour within the Si channel and estimate the related mobility gain. Sensitivity analyses of the simulation results using factorial designs and response surface methodology indicate that stresses within the Si channel are induced by a bending force determined by the extension of the poly width. A significant enhancement in mobility gain is found when an extended poly width combined with proper arrangements of the device geometry is applied.

The adoption of shallow trench isolation (STI) integrated with a contact etching stop layer (CESL) is regarded as an important technique in strain engineering that significantly boosts transistor mobility of nanoscale devices because the node technology of the metal-oxide-semiconductor field-effect transistor (MOSFET) is continually scaled down to 22 nm and lower. A finite element method based on stress simulation is implemented in this research to investigate the effects of STI geometric profiles on n-type MOSFET performance. The mechanism for transferring STI and CESL intrinsic stresses under the aforementioned conditions to the silicon (Si) channel is explained by considering the major procedures of process-induced stress. Results indicate that the approaches of suitable sunken STI patterns are more useful than those of a flat STI prototype because a difference in the resultant stress distribution for the Si channel region is introduced by the device profiles. The piezoresistance effect of Si is being actively explored at present to improve the characteristic of transistors because this effect has been extensively used in mechanical stress technology. A crystal strain resulting in a change in electrical conductivity is observed because of the aforementioned piezoresistance effect. Induced mobility gains from STI and CESL stressors are systematically observed. Integrating a tensile CESL and an STI stressor region results in almost 10% to 20% enhancement in carrier mobility.