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In semiconductor fabs, electron microscopes are key equipment for metrology, failure analysis, physical characterization and defect review classification. In a wafer fab like ST Crolles 300mm, CDSEMs are generating more than 20 Million of images per year. The image is by itself a raw material on which the metrology is performed. It is needed to get access to CD which is very often a single value extracted. If the CD is in specification, it is very unlikely that someone will look at the picture. If someone would do so in a systematic way, it would see that there is much more information available in the image than a single CD value. Unfortunately, most of this information passes under the radar of SPC charts and is somehow wasted. This paper presents results obtained by CDSEM image contour analysis from various kind of technologies and applications in manufacturing in our fab. These results show that images contain significant amounts of information that can be extracted and analyzed using an efficient contour extraction and analysis toolbox. Process variability of complex shapes can be shown, robust layer to layer metrics can be computed, pattern shifting, shape changes, image quality and many others too. This opens new possibilities for process control and process variability monitoring and mitigation.

With these proceedings we present μ-diffraction-based overlay (μDBO) targets that are well below the currently supported minimum size of 10×10 μm2 . We have been capable of measuring overlay targets as small as 4×4 μm2 with our latest generation YieldStar system. Furthermore we find an excellent precision (TMU < 0.33 nm for 6 × 6 μm2 ) without any compromise on throughput (MAM time < 60 ms). At last a study that compares four generations of YieldStar systems show clearly that the latest generation YieldStar systems is much better capable of reading small overlay targets such that the performance of a 16 × 16 μm2 on an early generation YieldStar 2nd-gen is comparable to that of a 8 × 8 μm2 on the latest YieldStar 5th-gen. This work enables a smaller metrology footprint, more placement flexibility and in-die overlay metrology solutions.

Continuous tightening of the overlay control budget in the semiconductor industry drives the need for improved overlay metrology capabilities. In this context, measurement accuracy needs to be addressed. The first part this study shows that Diffraction Based Overlay metrology accuracy can be improved with a dedicated methodology. This methodology involves the use of target design simulation software in order to maximize stack sensitivity and to minimize processes non uniformity impact on the measurement. In the second part this study focuses on Holistic Metrology Qualification (HMQ) methodology that allows selecting the best on-wafer target. The methodology is explained and discussed. It is demonstrated that HMQ helps to reduce target asymmetry impact on measurement uncertainty and to select primary recipe parameters (wavelength, polarization, etc…). Finally CD-SEM measurements were used to validate methodology results.

Patterning process control of advanced nodes has required major changes over the last few years. Process control needs of critical patterning levels since 28nm technology node is extremely aggressive showing that metrology accuracy/sensitivity must be finely tuned. The introduction of pitch splitting (Litho-Etch-Litho-Etch) at 14FDSOInm node requires the development of specific metrologies to adopt advanced process control (for CD, overlay and focus corrections). The pitch splitting process leads to final line CD uniformities that are a combination of the CD uniformities of the two exposures, while the space CD uniformities are depending on both CD and OVL variability. In this paper, investigations of CD and OVL process control of 64nm minimum pitch at Metal1 level of 14FDSOI technology, within the double patterning process flow (Litho, hard mask etch, line etch) are presented. Various measurements with SEMCD tools (Hitachi), and overlay tools (KT for Image Based Overlay – IBO, and ASML for Diffraction Based Overlay – DBO) are compared. Metrology targets are embedded within a block instanced several times within the field to perform intra-field process variations characterizations. Specific SEMCD targets were designed for independent measurement of both line CD (A and B) and space CD (A to B and B to A) for each exposure within a single measurement during the DP flow. Based on those measurements correlation between overlay determined with SEMCD and with standard overlay tools can be evaluated. Such correlation at different steps through the DP flow is investigated regarding the metrology type. Process correction models are evaluated with respect to the measurement type and the intra-field sampling.

Critical dimension and overlay measurements have become a key challenge in microelectronics process control, and the weight of metrology in the success of a patterning technique is increasing. For the 14 nm node, the limit of scanner resolution can be overcome by double patterning, which requires a maximum overlay variability of 3 nm between the two reticles of the first metal level. In the double patterning case of metal layers, critical dimension of line spaces and overlay are no longer independent. In this paper, the possibility of a common measurement after the second lithography is studied. Scatterometry has been used to fit successfully the critical dimension of the two sublevels. As sensitivity to overlay is too low in device-like target, a strategy has been implemented from diffraction-based overlay measurement. So it becomes possible to provide information on the lithography step quality before the second etch process to enable rework if necessary. Finally a scatterometry target has been designed to fit simultaneously the two critical dimensions and overlay. This target, which is designed to maximize overlay sensitivity, has been placed in the next 14 nm CMOS product and is expected to make this scatterometry method even more attractive.

Scatterometry mark design for improvement of the metrology performance is investigated in this joint work by ASML and STMicroelectronics. The studied marks are small, enabling metrology within the device area. The new mark-design approach reduces the effects from the mark-edges during the metrology measurement. For this, small assist-features are integrated in the mark design on the wafer. Thereby the new designs: 1. enlarge the metrology measurement-window, 2. optimize the repeatability and accuracy of the metrology at given mark size, 3. allow added functionality to existing marks within the current mark area, such as monitoring process asymmetry or multiple layer information, 4. allow for mark miniaturization at equal performance, enabling intra-field positioning. With this metrology tool-optical proximity correction (MT-OPC) included in the mark design, the metrology window is enhanced, while improved on-product overlay performance is obtained.

In microelectronics the two crucial parameters for the lithography step are the critical dimension, which is the width of the smallest printable pattern, and the misalignment error of the reticle, called overlay. For the 14 nm node, the limit of scanner resolution can be overcome by the double patterning technique, which requires a maximum overlay error between the two reticles of 3 nm [1] . The current approach in the measurements of critical dimension and overlay is to treat them separately, but it has become much more complex in the double patterning context, since they are no longer independent. In this paper, a strategy of a common measurement is developed. The aim of the strategy is to measure simultaneously overlay and critical dimension in the metal level double patterning grating before the second etch process. The scatterometry technique is well known for critical dimension measurement. This study demonstrates that the overlay between the two gratings can also be deduced. Thanks to this original scatterometry-based method, it becomes possible to provide information on the lithography step quality before the second etch process; therefore the lithography can be reworked if it is necessary.

Continued tightening of overlay control budget in semiconductor lithography drives the need for improved metrology capabilities. Aggressive improvements are needed for overlay metrology speed, accuracy and precision. This paper is dealing with the on product metrology results of a scatterometry based platform showing excellent production results on resolution, precision, and tool matching for overlay. We will demonstrate point to point matching between tool generations as well as between target sizes and types. Nowadays, for the advanced process nodes a lot of information is needed (Higher order process correction, Reticle fingerprint, wafer edge effects) to quantify process overlay. For that purpose various overlay sampling schemes are evaluated: ultra- dense, dense and production type. We will show DBO results from multiple target type and shape for on product overlay control for current and future node down to at least 14 nm node. As overlay requirements drive metrology needs, we will evaluate if the new metrology platform meets the overlay requirements.

One of the main challenges for lithography step is the overlay control. For the advanced technology node like 28nm and 14nm, the overlay budget becomes very tight. Two overlay techniques compete in our advanced semiconductor manufacturing: the Diffraction based Overlay (DBO) with the YieldStar S200 (ASML) and the Image Based Overlay (IBO) with ARCHER (KLA). In this paper we will compare these two methods through 3 critical production layers: Poly Gate, Contact and first metal layer. We will show the overlay results of the 2 techniques, explore the accuracy and compare the total measurement uncertainty (TMU) for the standard overlay targets of both techniques. We will see also the response and impact for the Image Based Overlay and Diffraction Based Overlay techniques through a process change like an additional Hardmask TEOS layer on the front-end stack. The importance of the target design is approached; we will propose more adapted design for image based targets. Finally we will present embedded targets in the 14 FDSOI with first results.

In microelectronics, the increase of component density is the main solution to improve circuit performance. The size of the patterns defined by lithography is reduced at each change of technology node. From the 14 nm node, optical lithography is facing the resolution limit for metal levels. In order to overcome this hurdle, metal levels are designed in two successive steps of patterning, which is composed of lithography followed by etching. This double patterning technique requires an appropriate metrology since overlay between the two steps and critical dimensions are directly linked. The developed method is based on scatterometry and overlay measurement by diffraction. Using a simulation code, the measurement targets have been designed optimally. Then the adopted method has been validated experimentally., En microélectronique, l'augmentation de la densité des composants est la solution principale pour améliorer la performance des circuits. Ainsi, la taille des structures définies par la lithographie diminue à chaque changement de nœud technologique. A partir du nœud 14 nm, la lithographie optique est confrontée à la limite de résolution pour les niveaux métalliques. Pour surmonter cet obstacle, les niveaux métalliques sont conçus en deux étapes successives de patterning regroupant chacune une étape de lithographie et une étape de gravure. Cette technique, nommée double patterning, requiert une métrologie adaptée car l'alignement entre les deux étapes et les dimensions critiques sont alors directement liées. La méthode de mesure développée dans cette thèse repose sur la scattérométrie et la mesure de l'alignement par diffraction. Un code de simulation a permis d'optimiser la conception des mires de mesure. De plus, la méthode de mesure adoptée a pu être validée expérimentalement.