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In this work the initial performance studies of the first small monolithic pixel sensors dedicated to charged particle detection, called CE-65, fabricated in the 65 nm TowerJazz Panasonic Semiconductor Company are presented. The tested prototypes comprise matrices of 64 × 32 square analogue-output pixels with a pitch of 15 μm. Different pixel types explore several sensing node geometries and amplification schemes, which allows for various biasing voltage of the detection layer and hence depletion conditions and electric field shaping. Laboratory tests conducted with a 55Fe source demonstrated that the CE-65 sensors reach equivalent noise charge in the 15 to 25 e− range and excellent charge collection efficiencies. Charge sharing is substantial for standard diodes, but can be largely suppressed by modifying their design. Depletion of the thin sensitive layer saturates at a reverse diode bias of about 5 V.

We present a 3.2-Gb/s serial link transmitter for MAPS application in future subatomic physics experiments. The transmitter features the inclusion of Reed–Solomon codes to achieve low transmission error rate. A CML driver with pre-emphasis in the transmitter allows serial transmission over low mass cables. The critical digital circuits are triplicated to resist SEU. The transmitter is fabricated in a 0 . 18 μ m CMOS Technology. A power consumption of 135 mW was measured at a typical setting. A frame data rate of 3 ⋅ 1 0 − 12 with confidence level of 94.5% was obtained through a FPGA based receiver, corresponding to a payload BER of 1 . 2 ⋅ 1 0 − 14 with confidence level of 94.9%. The transmitter functions well after being irradiated with 4.5 Mrad TID.

International audience; On the vertex detector of the International Linear Collider, a large number of hits are generated by the charged particles coming from the beam background. These charged particles produce large angles of incidence and generate elongated clusters. The CMOS pixel sensor (CPS) which would contain on-chip artificial neural networks could tag and remove these clusters to reduce the data flow of the detector system. The clustering procedure is the first step of data preprocessing. The conventional clustering algorithm is not suitable for on-chip integration since it requires sequential and iterative processing. In this article, a 2-D real-time clustering algorithm is proposed. The clustering algorithm is tested by 4500 frames of pixel values (12 bit/pixel) from MIMOSA-18. The clustering algorithm is implemented using Very High-Speed Integrated Circuit Hardware Description Language (VHDL), synthesized for different windows, multiplexers, and analog-to-digital converter (ADC) resolution. Power consumption and the occupied surface of the clustering implementation are presented. This implementation provides a possibility to integrate the clustering procedure into a CPS.

International audience; A detector prototype based on MAPS (monolithic active pixel sensor) is under development for the upgrade of the BESIII inner tracker. Pixel detector ladders with low material budget and high chip position precision are being developed. Each ladder consists of ten MIMOSA28 chips thinned to 50 μm , a flex cable and a carbon fibre support. In order to verify the design and quantify the performance of the ladders in terms of the spatial resolution, the detection efficiency, the gap between the neighbouring chips on the ladder and the material budget of the ladder, a detector prototype system was set up and tested at the T24 beamline at DESY. The system consists of five layers of ladders, readout electronics and data acquisition. The test results show that the spatial resolution is about 5 μm , and a tracking efficiency of 96% is achieved, the loss of about 4% of the efficiency most likely coming from the readout and the DAQ system. The average gap between the active areas of the neighbouring chips is about 380 μm . The actual gap and the chip location accuracy is better than 10 μm if the insensitive part of the chip is taken into account. The material budget of one ladder is 0.35 ± 0.03 (sys.)% X0 , which is consistent with the predicted value of 0.37% X0 . These test results validate a good performance of the prototype.

Over the last three decades, Monolithic Active Pixel Sensors (MAPS) have been developed to be used in several high-energy physics experiments [1–3]. The fact that no additional detector is required minimizes the material budget, reduces the fabrication cost and simplifies the integration procedure. Since the MAPS are designed in a standard CMOS (Complementary Metal Oxide Semi-conductor) technology, the design flow is also simplified. In the first MAPS, the charge generated in the undepleted sensitive volume diffused in all directions and was sensed on the collecting diodes. Spread of the charge over several pixels and slow charge collection due to the diffusion are the limiting factors for applications where the fast collection is necessary or charge sharing is not acceptable. However, few years ago, the trend in MAPS production moved to the fabrication of sensors with high-resistivity epitaxial layers. Several applications in high-energy physics were at the core of this development. Thanks to the fact that the epitaxial layer is highly resistive it can be depleted with a moderate voltage. This fact makes this new kind of sensors capable of detecting the low energy X-rays (

International audience; CMOS Pixel Sensors have been used in subatomic physics experiments for charged particles detection. In the International Linear Collider (ILC) vertex detector, the occupancy will be mainly driven by impacts coming from the beam background. This will have a huge impact to the data flow of the system. We propose a design of CMOS pixel sensors with on-chip Artificial Neural Network (ANN) to tag and remove these hits. It is based on different features of hits clusters. In this paper, we will describe the structure of an ANN implemented in an FPGA device. We will show and analyze the distribution of incident angles reconstructed by the ANN.

IMIC is a Monolithic Active Pixel Sensor prototype designed for the MAPSSIC project, which aims at developing wireless intracerebral probes dedicated to image positron-emitting source activity in the brain of awake and freely moving rats. Former experiments with the PIXSIC positron probe based on a passive sensor have validated the proof of concept, but have also shown limitations with regards to the probe robustness and to its transparency to annihilation photons. The IMIC circuit features a matrix of 16 × 128 active pixels of 30 × 50 µm2 size and targets to overcome the PIXSIC probe drawbacks by exploiting a thin sensitive layer of 18 µm, still featuring an overall thickness close to 300 µm. Additionally, by using a low power (55 nW/pixel) in-pixel front-end architecture providing binary output, IMIC solves the challenge of implanting an active sensor in tissues where overheating is forbidden. The needle-shaped sensor 610 µm × 12000 µm was fabricated and tested in laboratory. The whole sensor dissipates 160 µW and its imaging capabilities were asserted with various sources: 55Fe, 90Sr and 18F. These tests also demonstrated robust count-rate measurement with IMIC in the range 10–1000 counts/matrix/s. Finally, a dedicated setup qualitatively confirmed excellent in-sensitivity to 511 keV γ -rays. In this paper, we present the sensor requirements and its detailed design. We also discuss the first characterisation results and the outlook for the integration of IMIC into an implantable probe.

CMOS pixel sensors (CPS) have demonstrated performances meeting the specifications of the Interna- tional Linear Collider (ILC) vertex detector (VTX). This paper presents a low-power and small-area 4-bit column-level analog-to-digital converter (ADC) for CMOS pixel sensors. The ADC employs a self-timed trigger and completes the conversion by performing a multi-bit/step approximation. As in the outer layers of the ILC vertex detector hit density is of the order of a few per thousand, in order to reduce power consumption, the ADC is designed to work in two modes: active mode and idle mode. The ADC is fabricated in a 0.35 μm CMOS process with a pixel pitch of 35 μm. It is implemented with 48 columns in a sensor prototype. Each column ADC covers an area of 35 545 μm 2 . The measured temporal noise and Fixed Pattern Noise (FPN) are 0.96 mV and 0.40 mV, respectively. The power consumption, for a 3 V supply and 6.25 MS/s sampling rate, is 486 μW during idle time, which is by far the most frequently employed one. This value rises to 714 μW in the case of the active mode. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.49/0.28 LSB and 0.29/0.20 LSB, respectively. & 2014 Elsevier B.V. All rights reserved.

CMOS pixel sensors (CPS) for the future linear collider vertex detector (VXD) have strict requirements on their analog readout electronics, particularly on the analog-to-digital converter (ADC). This paper presents a low-power and small-area 4-bit column-level ADC for the CMOS pixel sensor, foreseen to equip the outer layers of the VXD. The ADC employs a self-triggered timing and completes the conversion by performing a multi-bit/step approximation. Accounting the fact that in the outer layers, the hit density is in the order of a few per thousand, this ADC is designed to operate in two modes: active mode and inactive mode. The average energy and total capacitance are significantly reduced by a power-gating control and a switching network, respectively. The ADC is fabricated in a ${\hbox{0.35}}~\mu\hbox{m}$ CMOS process with a pixel pitch of ${\hbox{35}}~\mu\hbox{m} $ . It is implemented with 48 columns in a sensor prototype. Each column ADC occupies an area of $ 35\times 545~\mu\hbox{m}^2$ . The measured temporal noise and fixed pattern noise (FPN) are 0.94 and 0.30 mV, respectively. The power consumption, at a 3-V supply and 6.25-MS/s sampling rate, equals to ${\hbox{486}}~\mu\hbox{W}$ in its inactive mode, which is by far the most frequent. This value rises to ${\hbox{714}}~\mu\hbox{W}$ in case of the active mode. These computations indicate an average power consumption of each column in the order of ${\hbox{487}}~\mu\hbox{W}$ , assuming a typical occupancy of $ \sim {\hbox{0.5}}\%$ in the whole sensor. Its DNL and INL are 0.49/-0.28 and 0.29/-0.20 least significant bit, respectively.

The apparatus of the ALICE experiment at CERN will be upgraded in 2017/18 during the second long shutdown of the LHC (LS2). A major motivation for this upgrade is to extend the physics reach for charmed and beauty particles down to low transverse momenta. This requires a substantial improvement of the spatial resolution and the data rate capability of the ALICE Inner Tracking System (ITS). To achieve this goal, the new ITS will be equipped with 50 μ m thin CMOS Pixel Sensors (CPS) covering either the three innermost layers or all the 7 layers of the detector. The CPS being developed for the ITS upgrade at IPHC (Strasbourg) is derived from the MIMOSA 28 sensor realised for the STAR-PXL at RHIC in a 0.35 μ m CMOS process. In order to satisfy the ITS upgrade requirements in terms of readout speed and radiation tolerance, a CMOS process with a reduced feature size and a high resistivity epitaxial layer should be exploited. In this respect, the charged particle detection performance and radiation hardness of the TowerJazz 0.18 μ m CMOS process were studied with the help of the first prototype chip MIMOSA 32. The beam tests performed with negative pions of 120 GeV/c at the CERN-SPS allowed to measure a signal-to-noise ratio (SNR) for the non-irradiated chip in the range between 22 and 32 depending on the pixel design. The chip irradiated with the combined dose of 1 MRad and 10 13 n eq / cm 2 was observed to yield an SNR ranging between 11 and 23 for coolant temperatures varying from 15 °C to 30 °C. These SNR values were measured to result in particle detection efficiencies above 99.5% and 98% before and after irradiation, respectively. These satisfactory results allow to validate the TowerJazz 0.18 μ m CMOS process for the ALICE ITS upgrade.

A CMOS sensor chip for charged particle detection has been developed and submitted for fabrication in a 0.18 μm Quadruple-Well (N&P-Wells, Deep N&P-Wells) CMOS Image Sensor (CIS) process. Improvement of the radiation hardness, the power dissipation and the readout speed of the mainstream CMOS sensors is expected with the exploration of this process. In order to ensure better charge collection and neutron tolerance, wafers with high-resistivity epitaxial layer have been chosen. In this paper a digital CMOS sensor prototype developed in order to validate the key analog blocks (from sensing element to 1-bit digital conversion) of a binary Monolithic Active Pixel Sensor (MAPS) in this process will be presented. The digital sensor prototype comprises four different sub-arrays of 20 μm pitch 64 × 32 pixels, 128 column-level auto-zeroed discriminators, a sequencer and an output digital multiplexer. Laboratory tests results including the charge-to-voltage conversion factor, the charge collection efficiency, the temporal noise and the fixed-pattern noise are presented in details. Some irradiation results will also be given.

In order to exploit the ability to integrate a charge collecting electrode with analog and digital processing circuitry down to the pixel level, a new type of CMOS pixel sensors with full CMOS capability is presented in this paper. The pixel array is read out based on a column-parallel read-out architecture, where each pixel incorporates a diode, a preamplifier with a double sampling circuitry and a discriminator to completely eliminate analog read-out bottlenecks. The sensor featuring a pixel array of 8 rows and 32 columns with a pixel pitch of 80 μ m × 16 μ m was fabricated in a 0.18 μ m CMOS process. The behavior of each pixel-level discriminator isolated from the diode and the preamplifier was studied. The experimental results indicate that all in-pixel discriminators which are fully operational can provide significant improvements in the read-out speed and the power consumption of CMOS pixel sensors.

The crosstalk between CMOS pixel sensors (CPS) degrades the performances of detector systems. Moreover, power distribution becomes a challenge in the future detectors for high energy physics experiments. In order to address these problems, a power management is proposed. Power supply voltages and reference voltages are internally generated in CPS. Two full on-chip linear regulators are proposed in this paper. Low area, low power consumption and low noise are achieved by a novel structure. The regulators have been designed and fabricated in a 0.35-μm commercial process. The measurement results are also presented.

In order to resolve the inherent readout speed limitation of traditional 2D CMOS pixel sensors, operated in rolling shutter readout, a parallel readout architecture has been developed by taking advantage of 3D integration technologies. Since the rows of the pixel array are zero-suppressed simultaneously instead of sequentially, a frame readout time of a few microseconds is expected for coping with high hit rates foreseen in future collider experiments. In order to demonstrate the pixel readout functionality of such a pixel sensor, a 2D proof-of-concept chip including a novel pixel-level signal processing chain was designed and fabricated in a 0.13 μ m CMOS technology. The functionalities of this chip have been verified through experimental characterization.

IMIC is a Monolithic Active Pixel Sensor prototype for the MAPSSIC project dedicated to direct detection of low energy β+ rays in the brain of awake and freely-moving rats using CMOS technology. Former experiments using a β+ Si probe developed within the PIXSIC project validated a methodological proof of concept. However, conducting routinely such measurements would require improvements with respect to the passive pixel sensors employed in PIXSIC. The new IMIC circuit is fabricated in a 180 nm CMOS Image Sensor Technology and features a matrix of 16 × 128 pixels, which are 30 × 50 μm2 large. The sensor has a needle-like aspect ratio (610 μm × 12 000 μm). The chip is produced on a 18 μm high-resistivity epitaxial layer substrate. The foreseen application requires high sensitivity to β-rays while being immune to background γ-rays. Another severe constraint is the limited power dissipation in order to minimize the thermal impact on the brain. IMIC is a fully-programmable digital sensor. The pixel design is based on the front-end architecture of the ALPIDE chip. However modifications have been made to store the information inside fired pixels between two readouts allowing low data throughput. The circuit is controlled through the SPI protocol, which allows for setting all the necessary polarization signals. The results of post-layout simulations show a high signal to noise ratio (>40) and low power dissipation of 115 μW/matrix. Laboratory characterization using β-rays validate these predictions and demonstrated that the slow readout can cope with the expected low activity (≍ 120 hits/matrix/s).

The development of CMOS Pixel Sensors (CPS) for charged particles detection had led to promising applications for dosimetry. Based on our previous studies on the detection of fast and thermal neutrons with a CMOS sensor originally designed for particle tracking in high energy physics, a dedicated integrated CMOS sensor for efficient neutron counting is presented. This sensor has been designed and fabricated in a [email protected] CMOS process. It is a low noise, low power consumption sensor with a sensitive area of 6.55mm^2 and a digital output. The test results indicate that it is suitable for neutron detection, thanks to its equivalent input noise charge of less than 400e^-, and a 20kHz detection frequency. In this paper the prototype is presented for both its circuit design and test results.

In order to solve the power distribution problem of detectors in high energy physics experiments, a full on-chip regulator is presented in this paper. It provides the analog power supply for CMOS pixel sensors. The maximum load current is 200 mA. The proposed regulator is stable in the full range of load current by introducing a zero and adapting the locations of poles and zeros. The compensation capacitance and resistance are significantly decreased to achieve low area. The chip area is only 0.044 mm2 excluding the bias and bandgap circuit, which can be shared with the other blocks in CMOS pixel sensors. The experimental results show that the output noise spectral density is less than 340 n VRMS/√Hz and 62 n VRMS/√Hz at 1 kHz and 100 kHz, respectively. The power consumption is 1.04 mW at the voltage of 3.3 V, when the load current is 200 mA.

A high-performance CMOS charge pump supply-noise-insensitive phase-locked loop (SNI-PLL) for on-chip clock generation of Monolithic Active Pixel Sensors (MAPS) is presented. The SNI-PLL employs a voltage regulator which provides two stable power supplies to the charge pump and the voltage-controlled oscillator (VCO), respectively. The voltage regulator achieves a Power Supply Noise Rejection (PSNR) of -40 dB over the entire frequency spectrum by using virtual grounded cascode compensation technique. The presented SNI-PLL generates a 160 MHz clock with a Time Interval Error (TIE) of 0.062 UI (Unit Interval) from a 10 MHz reference clock in a noisy power supply environment. The circuit was fabricated with a 0.35 μ m standard CMOS process and occupies 0.38 mm 2 area. The power consumption of the SNI-PLL is about 15.2 mW at 160 MHz.

This paper presents a novel design of an integrated 12-bit multi-channel single-slope ramp analog-to-digital converter (ADC) for a small animal positron emission tomography(PET) imaging system. The proposed ADC is a part of a monolithic front-end readout application-specific integrated circuit(ASIC) which is dedicated to the detector modules consisting of LYSO scintillation crystals read out on both sides by the multi-channel plate (MCP) photodetectors. The function of the ADC is to digitize the voltage signals from a large number of readout channels. Digital delay-locked loop (DLL) techniques are proposed to realize time interpolations in order to reduce the conversion time and to enhance the resolution. Both high precision and low power are obtained. An eight-channel prototype chip is implemented in AMS 0.35 μm CMOS technology. The available resolution of the ADC is 9 ~ 12 bits. The maximum DNL and INL of the fine conversion in the ADC is ±0.75 LSB and ±0.5 LSB, respectively. The static power consumption of the ADC is 3 mW + 0.2 mW/Channel. This ADC architecture provides a possibility to integrate low-noise front-end readout circuits, time-to-digital converters and ADC together into a monolithic ASIC and to output both the energy quantity and the time information with digital representations for PET imaging systems.

This paper presents the design and characteristics of a mixed-signal 64-channel front-end readout ASIC called IMOTEPAD dedicated to multi-channel plate (MCP) photodetector coupled to LYSO scintillating crystals for small-animal PET imaging. In our configuration, the crystals are oriented in the axial direction readout on both sides by individual photodetector channels allowing the spatial resolution and the detection efficiency to be independent of each other. As a result, both energy signals and timing triggers from the photodetectors are required to be read out by the front-end ASIC. This dedicated ASIC IMOTEPAD comprises two parts: the analog part IMOTEPA and the digital part IMOTEPD. The IMOTEPA is dedicated to energy measurement. And the timing information is digitized by the IMOTEPD in which the key principal element is a time-to-digital converter (TDC) based on a delay-locked loop (DLL) with 32 delay cells. The chip is designed and fabricated in 0.35 μm CMOS process. The measurements show that for the analog part IMOTEPA, the energy gain is 13.1 mV/pC while the peak time of a CR-RC pulse shaper is 280 ns. The SNR is 39 dB and the RMS noise is 300 μV. The nonlinearity is less than 3%. The crosstalk is less than 0.2%. For the IMOTEPD, the bin size of the TDC is 625 ps with a reference clock of 50 MHz. The RMS jitter of the DLL is less than 42 ps. The DNL of the TDC is equal to about 0.17 LSB and the INL is equal to 0.31 LSB. The power dissipation of each channel is less than 16.8 mW. The design of the ASIC, especially for TDC and the measurement results of the IMOTEPAD will be presented and discussed in this paper.

In the framework of the EUDET-JRA1 project (European Detector R&D towards the International Linear Collider), which consists of design, realization and implantation of a high resolution beam digital telescope, based on Monolithic Active Pixel Sensors (MAPS), an intermediate digital chip sensor, MIMOSA22, has already been delivered with good detection performances. Although this intermediate chip has fulfilled all the initial requirements of the project, it was admitted that radiation tolerance behavior of the sensor could be improved, especially if the high precision telescope is used later in a hadron testbeam infrastructure. For this purpose, a new version of the sensor, MIMOSA22-BIS, has been designed, with several improved pixel architectures, and using the same AMS 0.35 μm opto process of the sensor MIMOSA22. This paper will be focused on tests performed in laboratory conditions using a 55Fe source, and tests performed in CERN-SPS, using a 120 GeV pion beam, in order to characterize detection performances of the chip with MIPs, before and after ionizing irradiation.

This paper represents the design of a low-noise, wide band multi-channel readout integrated circuit (IC) used as front-end readout electronics of Avalanche Photo Diodes (APD) dedicated to a small animal Positron Emission Tomography (PET) system. The first 10-channel prototype chip (APD_Chip) of the analog parts has been designed and fabricated in a 0.35-μm CMOS process. Every channel of the APD_Chip includes a charge-sensitive preamplifier (CSA), a CR-(RC)2 shaper, and an analog buffer. In each channel, the CSA reads charge signals (10 bits dynamic range) from an APD array having 10 pF of capacitance per pixel. A linearized degenerated differential pair which ensures high linearity in all dynamical range is used as the high feedback resistor for preventing pile up of signals. The designed CSA has the capability of compensating automatically up to 200 nA leakage current from the detector. The CR-(RC)2 shaper filters and shapes the output signal of the CSA. An equivalent input noise charge obtained from test is 275 e? + 10 e?/pF. In this paper the prototype is presented for both its circuits design and its test results.

This paper presents design techniques of a multiphase clock generator using a low-jitter delay-locked loop (DLL) or its array for the developments of high-resolution multi-channel time-to-digital converters (TDCs). The low-jitter technologies for both a single DLL and an array of DLL are discussed. Based on the previous work on the design of a single DLL with 32 delay cells, an array of mixed-mode low-jitter DLLs is proposed for achieving smaller time taps. The array of DLL is successfully designed and embedded into a prototype chip of a three-channel high-resolution TDC in 0.35 CMOS process. The operational range of the DLL in the array is from 50 MHz to 120 MHz. The RMS value of measured cycle-to-cycle jitter in the DLL is about 7 ps while the peak-to-peak value is about 20 ps. A bin size of 71 ps can be achieved by using a reference clock of 100 MHz. The DNL and INL of the evaluated chip are 0.58 LSB and 0.63 LSB, respectively. The static power dissipation of the DLL array is about 23 mW.

In this paper, a new design of on-chip CMOS voltage regulator, which provides two stable power supplies to charge pump and voltage controlled oscillator (VCO) in charge pump phase-locked loop (PLL), is presented. A power supply noise rejection (PSNR) whose peaking is less than -40dB is achieved over the entire frequency spectrum for VCO supply. The voltage regulator provides maximum 14mA current, and static current is about [email protected] at 3.3V. Based on the proposed voltage regulator, a PLL clock generator has been developed and measured in the AMS [email protected] CMOS process. Operating at 160MHz, a period jitter of 13.64ps was measured under a clean power supply, while period jitter became 16.24ps under a power supply modulated with a 400mV, 10kHz square wave.

Most applications of future CMOS Monolithic Active Pixel Sensors (MAPS) require high-speed digital serial data link for data transmission. Commercial monolithic serial transmitters can be found that meet the bandwidth requirements of the MAPS. However, there is no available space for additional chips on the MAPS layers in the detector. To address this issue, a serial transmitter prototype, containing a phase-locked loop (PLL) clock generator, an 8B/10B encoder, a serializer and a low-voltage differential signaling (LVDS) driver was developed. Since the clock is embedded into the data by using serial transmission, the detector material budget due to data transmission is minimized. The serial transmitter prototype is integrated in a sensor chip, MIMOSA26, developed in IPHC (Institut Pluridisciplinaire Hubert-Curien, France). It has been implemented in a 0.35 ?m CMOS technology. This first serial transmitter prototype was designed aiming to transmit data at 160 Mbit/s. Measurements proved our design is fully functional.

A high resolution beam telescope, based on CMOS Monolithic Active Pixels Sensors (MAPS), is being developed under the EUDET collaboration, a coordinated detector R&D program for a future international linear collider. A very good spatial resolution < 5 mum, a fast readout time of 100 mus for the whole array (136 times 576 pixels) and a high granularity can be obtained with this technology. A recent fast MAPS chip, designed in AMS CMOS 0.35 mum Opto process with 14 mum epitaxial layer and called MIMOSA22, was submitted to foundry. MIMOSA22 has an active area of 26.5 mm2 with a pixel pitch of 18.4 mum arranged in an array of 576 rows by 136 columns where 8 columns have analog test outputs and 128 have their outputs connected to offset compensated discriminator stages. The pixel array is divided in seventeen blocks of pixels, with different amplification gain, diode size, pixel architecture and is addressed row-wise through a serially programmable (JTAG) sequencer. Discriminators have a common adjustable threshold with internal DAC. MIMOSA22 is the last chip (IDC-Intermediate Digital Chip), before the final sensor of the EUDET-JRA1 beam telescope, which will be installed on the 6 GeV electron beam line at DESY. In this paper, laboratory test results on analog and digital parts are presented. Test beam results, obtained with a 120 GeV pion beam at CERN, are also presented. In the last part of the paper, results on irradiated chips are given.

New applications for imaging are currently emerging in industrial and research systems: measurement of rare physical events, particle detection for high energy physics, electronic microscopy, etc. Imaging sensors are generally developed by using CCDs, CMOS technology or hybrid pixels. The originality of the CMOS Sensors or MAPS (Monolithic Active Pixel Sensors) presented in this paper is the integration of PhotoFETs into a pixel cell. The PhotoFET is a particle sensing element which implements (advantageously) an amplifying structure. Two different PhotoFETs structures realized in the AMS 0.35 μm technology will be presented. A theoretical study will explain the PhotoFETs architectures and its advantages compared to classical M.A.P.S ionizing particle detectors. The main characteristics of PhotoFETs structures measured in current mode are described in this paper.

Monolithic Active Pixel Sensors (MAPS) constitute a novel technique for silicon position-sensitive detectors. Their development is driven by highly demanding performances of the vertex detector foreseen at the future linear collider. This paper presents a new approach for a detector based on the MAPS principle. The pixel concept proposed is foreseen to match with signal discrimination implemented on the chip. It combines on-pixel signal amplification with double sampling operation, and provides a signal resulting from the difference between the charges collected in two consecutive time slots. The device can be fabricated in a cheap standard CMOS process, using a wafer made of a moderately doped medium. The new pixel design uses only NMOS transistors, nwell/psub and pdiff/nwell diodes and poly1-to-poly2 capacitors. It is based on a principle of switched operation circuits with 15 transistor switches close to the minimum size and 14 transistors used for the signal amplification.

This paper presents novel in-pixel amplifiers for CMOS pixel sensors. Two kinds of offset-compensated amplifiers allow the sensors to achieve a high signal-to-noise ratio. Based on theoretical analysis, the gain of the input offset-compensated amplifier is less sensitive to threshold voltage variation than the output offset-compensated amplifier. A 12 μ m pitch CMOS pixel sensor with the input offset-compensated amplifier was therefore designed and fabricated in a 0.13 μ m CMOS technology. Measurements indicate that the implementation of this amplifier can result in a high signal-to-noise ratio for a CMOS pixel sensor.

The APVD is a radiation-hard integrated circuit fabricated in DMILL technology and developed for the front-end electronic to read out the tracking detectors of CMS. This paper reports test results obtained with prototypes connected to silicon and Micro-Strip Gas Chambers (MSGC) detectors in a 200 GeV=c pion beam. A signal-to-noise ratio of 12 and 7, affected by residual excess noise from common mode oscillations, a spatial resolution of 7 and 11 mm and a detection efficiency of 98% and 93% were measured for silicon detectors in peak and deconvolution modes, respectively. With the MSGC detector, we obtained a signal-to-noise ratio of 17 and a detection efficiency of 97%. The response of an MSGC with this electronic has also been studied with perpendicular and inclined particle tracks and good agreement with a simulation of detector and electronic was obtained. r 2001 Elsevier Science B.V. All rights reserved. PACS: 85.40.� e

A high resolution beam telescope, based on CMOS monolithic active pixel sensors (MAPS), is being developed within the EUDET collaboration. Mimosa26 is the first pixel sensor covering an active area of ∼224 mm 2 with integrated zero suppression for this telescope. A single point resolution better than 4 μm is expected with a pixel pitch of 18.4 μm. The matrix is organised in 576 rows and 1152 columns. At the bottom of the pixel array, each column is connected to an offset compensated discriminator to perform the analogue to digital conversion. Digital data are then treated by a zero suppression circuit in order to send useful information. This architecture allows a fast readout frequency of ∼10 k frames/s. The paper concentrates on the details of the chip design and its main performances.

A detector, equipped with 50 um thin CMOS Pixel Sensors (CPS), is being designed for the upgrade of the Inner Tracking System (ITS) of the ALICE experiment at LHC. Two CPS flavours, MISTRAL and ASTRAL, are being developed at IPHC aiming to meet the requirements of the ITS upgrade. The first is derived from the MIMOSA28 sensor designed for the STAR-PXL detector. The second, which integrates a discriminator in each pixel, improves the readout speed and power consumption. This paper will describe in details the sensor development and show some preliminary test results.

This paper presents the design of a high accuracy multichannel peak detect and hold (PDH) circuit. This PDH measures the energy of an event and is one part of a readout chain for avalanche photo diodes (APD)-based positron emission tomography (PET) imaging. The circuit is designed in a 0.35μm CMOS process. The proposed PDH is dedicated to ultra low amplitude, large amplitude range from several tens millivolts to 1.1 V, and fast peaking time (190 ns) semi-Gaussian pulses. The two-phase technique has been used to cancel the major error source of the classical CMOS PDH: offset. A two-gain OTA is applied to minimize the DC error. A peak error less 1% for a small input signal (amplitude is between 40 mV and 300 mV) and a peak error less than 0.2% for a large input signal (amplitude is between 300 mV and 1.1 V) have been obtained from test. The area of a PDH is equal to about 200 μm × 40 μm. In our PDH system, the drop rate is negligible.

This paper presents the design and characteristics of a front-end readout application-specific integrated circuit (ASIC) dedicated to a multichannel-plate photodetector coupled to LYSO scintillating crystals. In our configuration, the crystals are oriented in the axial direction readout on both sides by individual photodetector channels allowing the spatial resolution and the detection efficiency to be independent of each other. Both energy signals and timing triggers from the photodetectors are required to be read out by the front-end ASIC. A current-mode charge-sensitive amplifier is proposed for this application. This paper presents performance characteristics of a 10-channel prototype chip designed and fabricated in a 0.35-μm complementary metal-oxide semiconductor process. The main results of simulations and measurements are presented and discussed. The gain of the chip is 13.1 mV/pC while the peak time of a CR-RC pulse shaper is 280 ns. The signal-to-noise ratio is 39 dB and the rms noise is 300 μV/√(Hz). The nonlinearity is less than 3% and the crosstalk is about 0.2%. The power dissipation is less than 15 mW/channel. This prototype will be extended to a 64-channel circuit with integrated time-to-digital converter and analog-to-digital converter together for a high-sensitive small-animal positron emission tomography imaging system.

CMOS Pixel Sensors tend to become relevant for a growing spectrum of charged particle detection instruments. This comes mainly from their high granularity and low material budget. However, several potential applications require a higher read-out speed and radiation tolerance than those achieved with available devices based on a 0.35 micrometers feature size technology. This paper shows preliminary test results of new prototype sensors manufactured in a 0.18 micrometers process based on a high resistivity epitaxial layer of sizeable thickness. Grounded on these observed performances, we discuss a development strategy over the coming years to reach a full scale sensor matching the specifications of the upgraded version of the Inner Tracking System (ITS) of the ALICE experiment at CERN, for which a sensitive area of up to about 10 square meters may be equipped with pixel sensors., Presented at the Vienna Conference on Instrumentation 2013 4 pages, 5 figures

This paper presents a CMOS Pixel Sensor (CPS) prototype for the outer layers of the future International Linear Collider (ILC) vertex detector. It is composed of a matrix of 48 × 64 pixels with a 4-bit column-parallel analog-to-digital converter (ADC). The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation in order to reduce the temporal and fixed pattern noise (FPN). The self-triggered ADC accommodating the pixel readout in a rolling shutter mode completes the conversion by performing a multi-bit/step approximation. The ADC design was optimized for power saving at sampling frequency. Accounting the fact that in the outer layers of the ILC vertex detector the hit density is in the order of a few per thousand, this ADC works in two modes: active mode and inactive mode. The average energy and total capacitance are significantly reduced by a power-gating control and a switching network, respectively. The prototype sensor was fabricated in a 0.35 μm CMOS process with a pixel pitch of 35 μm. The designed 4-bit ADC dissipates, at a 3-V supply and 6.25-MS/s sampling rate, 486 μW in its inactive mode, which is by far the most frequent. This value rises to 714 μW in case of the active mode. Its footprint amounts to 35 × 545 μm2.

This paper presents the design techniques of a monolithic multichannel front-end readout chip integrated with both high-accuracy TDC and high-resolution ADC for the PET using LYSO(Ce) crystals read out by MCP PMT at both ends. In the front-end readout chain, a regulated cascade (RGC) preamplifier is employed in every channel for amplifying the current signals generated from MCP detector. A gain-adjustment stage, an integrator and a pulse shaper are employed for pulse height analysis which changes the width of the pulses. A discriminator is placed after the preamplifier to generate triggers. These triggers are sent to a sub-nanosecond TDC for measurement and digitizing. The peak values of the shaped pulses are digitized by a multichannel time-based ADC for measurement. Three prototype chips are designed in AMS 0.35 μm CMOS technology. In the front-end readout prototype chip, the dynamic range, the linearity, and the power dissipation are optimized. The input dynamic range from few fC to more than 100 pC can be achieved. The analog output range of the front-end readout circuits is from 1.2 V to 3.2 V. The shaping time is 280 ns and the power dissipation is reduced to less than 15 mW. In the TDC chip based on a DLL array, the RMS jitter and the peak-to-peak jitter of the used DLL are reduced to 7 ps and 21 ps, respectively. The bin size of the TDC has been reduced to 71ps with a reference clock of 100 MHz. In the multichannel time-based ADC chip, a maximum resolution of 12 bits, a sampling rate of ∼1 MS/s, and the power dissipation of 3 mW ° 0.2 mW/channel are achieved.

This paper presents a novel digital delay-locked loop (DDLL) dedicated to generate multiphase delayed clocks for the development of the multi-channel analog-to-digital converters (ADCs) and/or time-to-digital converters (TDCs). The DDLL consists of a digital delay chain using linear delay elements, a Bangbang phase detector, a Up/Down counter and a digital filter. The digital filter is utilized to reduce digital ripples when DDLL is locked. A prototype chip of the proposed DDLL with 32 delay cells is designed and fabricated in AMS 0.35 µm CMOS process. The die area is 690 µm × 73 µm. For the DDLL core, the rms jitter and the peak-to-peak jitter of is 0 and 19.8 ps at 50 MHz clock. However, jitter-tolerant performances can be achieved when the DDLL core and the digital filter are used as a multiphase clock generator. The total power dissipation is about 3 mW.

In the framework of the EUDET-JRA1 project (European Detector R&D towards the International Linear Collider), which consists to design, realize and qualify a high resolution beam digital telescope, based on Monolithic Active Pixel Sensors (MAPS), an intermediate digital chip sensor, MIMOSA22, has already been delivered with good detection performances. Although this intermediate chip has fulfilled all the initial requirements of the project, it was admitted that radiation tolerance behavior of the sensor could be improved, especially if the high precision telescope is used later in a hadron testbeam infrastructure. For this purpose, a new version of the sensor, MIMOSA22-BIS, has been designed, with improvement of several pixel architectures, and using the same AMS 0.35 μm opto process of the sensor MIMOSA22. This paper will be focused on tests performed in laboratory, using a 55Fe source, and tests performed in CERN-SPS, using a 120 GeV pion beam, in order to characterize detection performances of the chip with MIPs, before and after ionizing irradiation.

The MIMOSA pixel sensors developed in Strasbourg have demonstrated attractive features for the detection of charged particles in high energy physics. So far, full-size sensors have been prototyped only with analog readout, which limits the output rate to about 1000 frames/second. The new MIMOSA 26 sensor provides a 2.2 cm2 sensitive surface with an improved readout speed of 10,000 frames/second and data throughput compression. It incorporates pixel output discrimination for binary readout and zero suppression micro-circuits at the sensor periphery to stream only fired pixel out. The sensor is back from foundry since february 2009 and has being characterized in laboratory and in test beam. The temporal noise is measured around 13-14 e− and an operation point corresponding to an efficiency of 99.5±0.1 % for a fake rate of 10−4 per pixel can be reached at room temperature. MIMOSA 26 equips the final version of the EUDET beam telescope and prefigures the architecture of monolithic active pixel sensors (MAPS) for coming vertex detectors (STAR, CBM and ILC experiments) which have higher requirements. Developments in the architecture and technology of the sensors are ongoing and should allow to match the desired readout speed and radiation tolerance. Finally, the integration of MAPS into a micro-vertex detector is addressed. A prototype ladder equipped, on both sides, with a row of 6 MIMOSA 26-like sensors is under study, aiming for a total material budget about 0.3% X 0 .