1. First Test Results of the Trans-Impedance Amplifier Stage of the Ultra-fast HPSoC ASIC
- Author
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Chock, C., Flood, K., Macchiarulo, L., Mostafanezhad, I., Perron, R., Uehara, D., Martinez-Mckinney, F., Rojas, A. Martinez, Mazza, S., Nizam, M., Ott, J., Ryan, E., Sadrozinski, H. F. -W., Schumm, B., Seiden, A., Shin, K., Tarka, M., Wilder, M., and Zhao, Y.
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Physics - Instrumentation and Detectors - Abstract
We present the first results from the HPSoC ASIC designed for readout of Ultra-fast Silicon Detectors. The 4-channel ASIC manufactured in 65 nm CMOS by TSMC has been optimized for 50 um thick AC-LGAD. The evaluation of the analog front end with \b{eta}-particles impinging on 3x3 AC-LGAD arrays (500 um pitch, 200x200 um2 metal) confirms a fast output rise time of 600 ps and good timing performance with a jitter of 45 ps. Further calibration experiments and TCT laser studies indicate some gain limitations that are being investigated and are driving the design of the second-generation pre-amplification stages to reach a jitter of 15 ps., Comment: 7 pages, 6 figures
- Published
- 2022
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