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We demonstrate source/drain (S/D) design for GaAs n-type metal-oxide-semiconductor field-effect transistor (NMOSFET) by embedding Ge into recessed S/D region to eliminate the intrinsic issues of the low solid solubility of dopants and low density of states (DOS) in GaAs material. For achieving high quality S/D epitaxy, the effects of substrate orientation and surface preparation on the quality of the epitaxial Ge film were investigated. High quality Ge film was successfully grown on the GaAs (111)A substrate by using a ultra high vacuum chemical vapor deposition (UHVCVD) tool and the significant improvement in the surface root-mean-square (RMS) roughness was observed as compared to that on the (100) substrate. The fabricated GaAs NMOSFET with hetero-Ge S/D exhibits an Ion/Ioff ratio of ∼2.5 × 102. Even though the performance can be further improved, we think our proposed scheme sheds the light on overcoming the issues of the low solid solubility of n-dopant and low DOS in III-V MOSFETs. © 2014 The Electrochemical Society. [DOI: 10.1149/2.016404jss] All rights reserved.

The selective growth of germanium into nanoscale trenches on silicon substrates was ext. 7660investigated. These nanoscale trenches–the smallest size of which was 50 nm–were fabricated using the state-of-the-art shallow trench isolation technique. The quality of the Ge films was evaluated using transmission electron microscopy. It was found that the formation of threading dislocations (TDs) was effectively suppressed when using this deposition technique. It was considered that for the Ge grown in nanoscale Si areas (e.g., several tens of nanometers), the TDs were readily removed during cyclic thermal annealing, predominantly because their gliding distance to the SiO2 sidewalls was very short. Therefore, nanoscale epitaxial growth technology can be used to deposit Ge films on lattice-mismatched Si substrates with a reduced defect density.

Short-channel controllability by insulating halo (IH) is investigated using the NFET strained-Si technology. By embedding SiO2/Si3N4 insulators in the halo regions, the increase of halo implant concentration reduces source/drain depths and improves short-channel effects such as drain-induced barrier lowering. With Ioff similar to the control device at the same gate length by adjusting the threshold voltage, the channel doping can be reduced, and the channel mobility increases due to the decrease of vertical electric field. Moreover, IHs reduce the shallow trench isolation compressive stress in the channel and yield a high-electron mobility enhancement. The device performance is optimized based on the simulation design. Up to a 23% Ion improvement was experimentally achieved by optimal IH insertion. A 7% lower junction capacitance and an 8% ring oscillator speed improvement are demonstrated when the IH is adopted in the NFET alone. Moreover, device reliability is carefully examined and is not adversely impacted by IH insertion.

Considerable on-state impact ionization and off-state tunneling leakages are the two principal drawbacks of InAs/AlSb HEMTs, which have a small bandgap and type-II band lineup. This work introduced a wide-bandgap high-k Al2O3 between the gate metal and semiconductor surface and successfully demonstrated DC and RF performance of the InAs/AlSb metal–oxide–semiconductor HEMTs (MOS-HEMTs). An MOS-HEMT device with a 2.0 μm gate length yields DC performance of IDSS = 286 mA/mm and Gm = 495 mS/mm and RF performance of fT = 10.1 GHz and fMAX = 19.9 GHz. Compared with a conventional HEMT, gate leakage is reduced by one order and the marked dependence of drain current on gate bias in the deep subthreshold region is largely alleviated.

Conventional InAs/AlSb HEMTs suffer from chemical instability in materials and high kink current. To avoid these drawbacks, this work proposes a novel layer structure of an InAsSb/AlSb HEMT and a novel two-step passivation process. Performance improvements are reduced dc output conductance by approximately 4.6 times at V DS = 0.5 V and I D = 100 mA/mm, and gate leakage to 1 × 10 −3 mA/mm from 4 at V GS = −1.2 V and V DS = 0.8 V compared with those of two InAs/AlSb HEMTs, one with the conventional one-step and the other with the proposed two-step passivation process. Both dc and rf performances show strong evidences of impact ionization suppression.

Extrinsic source/drain series resistance (R SD) is becoming inevitably dominant in state-of-the-art CMOS technologies as the intrinsic device resistance continues to scale with channel length dictated by the Moore's Law. As a result, advanced scaling techniques to achieve a lower intrinsic device resistance become less effective, particularly for NMOSFETs. With an attempt to better understand R SD impacts and identify the next key technology enabler, high-performance strained NMOSFETs featuring metallized (NiSi) source/drain extension (M-SDE) are investigated due to its cost-effective process and good short-channel scalability. The spacing between metallized extension and gate electrode edge is shown to play a very important role in R SD reduction and can significantly affect the electrical characteristics of M-SDE NMOSFETs. Tradeoff between R SD reduction and device integrity like junction leakage and reliability is found when the extension-to-gate edge spacing is modulated. On the other hand, by optimizing the NiSi-to-gate edge spacing, M-SDE NMOSFETs exhibit a higher on-current (I ON) and a higher strain sensitivity while maintaining comparable drain-induced barrier lowering, subthreshold swing, I OFF , and hot-carrier reliability as compared with the conventional SDE devices.

This paper reports the influences of uniaxial mechanical stress on the reverse-biased source/drain to substrate junction leakage of state-of-the-art 65 nm CMOS transistors. For n-channel metal-oxide-semiconductor (NMOS) transistors, the band-to-band tunneling (BTBT) dominates the junction leakage current due to heavily doped junction and pocket implants. However, for p-channel metal-oxide-semiconductor (PMOS) transistors with embedded SiGe source/drain, the leakage current is found to result from both BTBT and generation current due to defects generated in the SiGe layer and at the SiGe/Si interface. A four-point bending technique is used to apply mechanical uniaxial stress on NMOS and PMOS devices along the longitudinal direction. It was found that the leakage current of both devices increases (decreases) with applied uniaxial compressive (tensile) stress, and that the strain sensitivity of the junction leakage of NMOS transistors is much weaker than that of PMOS transistors. By combining the bending technique with process strained Si (PSS) technology, additional stress was applied to NMOS and PMOS with high built-in stress to investigate the characteristics of junction leakage under extremely high uniaxial stress. It is shown that uniaxial tensile stress can both enhance the NMOS device performance and decrease the junction leakage. However, for the PMOS, there exists a tradeoff between boosting the transistor performance and decreasing the junction leakage current, so there is a limit in the amount of compressive stress that can be beneficially applied.

The correlation between channel mobility gain (Deltamu), linear drain-current gain (DeltaIdlin), and saturation drain-current gain (DeltaIdsat) of nanoscale strained CMOSFETs are reported. From the plots of DeltaIdlin versus DeltaIdsat and ballistic efficiency (Bsat,PSS), the ratio of source/drain parasitic resistance (RSD,PSS) to channel resistance (RCH,PSS) of strained CMOSFETs can be extracted. By plotting Deltamu versus DeltaIdlin, the efficiency of Deltamu translated to DeltaIdlin is higher for strained pMOSFETs than strained nMOSFETs due to smaller RSD,PSS-to-RCH,PSS ratio of strained pMOSFETs. It suggests that to exploit strain benefits fully, the RSD,PSS reduction for strained nMOSFETs is vital, while for strained pMOSFETs the DeltaIdlin -to-Deltamu sensitivity is maintained until RSD,PSS becomes comparable to/or higher than RCH,PSS

Channel backscattering characteristics of uniaxially strained nanoscale CMOSFETs are reported for the first time. Channel backscattering ratio increases and decreases under uniaxial tensile and compressive strain, respectively. It is found that in sub-100-nm devices, strain-induced modulation of carrier mean-free path for backscattering and reduction in k/sub B/T layer thickness are responsible for the different behaviors of backscattering ratio. Nevertheless, the source-side injection velocity improves irrespective of the strain polarities. The impact of channel backscattering ratio on drive current is also analyzed in terms of ballistic efficiency and injection velocity.

We report the first realization of high performance Ge CMOS using a novel InAlP passivation scheme. The large conduction band and valence band offsets between InAlP and Ge confine electrons and holes within the Ge channel for n-FETs and p-FETs, respectively. The InAlP cap reduces scattering due to high-K/InAlP interface traps and boosts carrier mobility. As a result, a record high electron mobility μEFF of ~958 cm2/V·s at NINV of 6×1011 cm-2 was achieved for Ge(100) n-FETs, and a high peak hole mobility of ~390 cm2/V·s was obtained for Ge(100) p-FETs. High on-state currents ION of 39.5 μA/μm and 31.2 μA/μm were achieved at gate overdrive |VGS-VTH| = 1 V and |VDS| = 1 V for the n-FETs and p-FETs, respectively, with a gate length LG of ~3 μm. In addition, for the first time, this novel InAlP passivation technique was integrated into Ge n-FinFETs, and good control of short channel effects (SCEs) was achieved.

Spacer-less In 0.7 Ga 0.3 As n-MOSFETs with self-aligned Ni-InGaAs contacts formed using a direct reaction between Ni and InGaAs were demonstrated. A novel salicide-like metallization process was developed to achieve self-aligned Ni-InGaAs contacts, comprising the steps of Ni reaction with In x Ga 1−x As and selective removal of excess Ni. Dopantless n-MOSFETs with metallic Ni-InGaAs source/drain (S/D) and n-MOSFETs with Si-doped S/D and Ni-InGaAs contacts were compared. Si implant performed before the metallization effectively suppressed the off-state current I OFF by more than 10 times.

The optical properties of GaAs nano-wires grown on shallow-trench-patterned Si(001) substrates were investigated by cathodoluminescence. The results showed that when the trench width ranges from 80 to 100 nm, the emission efficiency of GaAs can be enhanced and is stronger than that of a homogeneously grown epilayer. The suppression of non-radiative centers is attributed to the trapping of both threading dislocations and planar defects at the trench sidewalls. This approach demonstrates the feasibility of growing nano-scaled GaAs-based optoelectronic devices on Si substrates.

We report the first demonstration of III–V n-MOSFETs with self-aligned contact technology. The self-aligned contact was formed using a salicide-like process which is compatible with CMOS process flow. A new epitaxy process was developed to selectively form a thin continuous germanium-silicon (GeSi) layer on gallium arsenide (GaAs) source and drain (S/D) regions. Nickel was deposited and annealed to form NiGeSi, and unreacted metal was removed. A second anneal diffuses Ge and Si into GaAs to form heavily n+ doped regions, and a novel self-aligned nickel germanosilicide (NiGeSi) ohmic contact was achieved. MOSFETs with the new self-aligned metallization process were realized.

Antimonide-based heterostructural p-channel HFET epitaxies consisting of an In 0.44 Ga 0.56 Sb quantum well located between AlSb barriers were developed by molecular beam epitaxy. The In 0.44 Ga 0.56 Sb channel layer was compressively strained to enhance hole mobility. Room-temperature Hall measurements to the as-grown materials exhibited a hole mobility as high as 895 cm2/V s. Ti/Pt/Au and Pt/Ti/Pt/Au metals were utilized in Schottky gate metallization processes for evaluating their effects on the device performance. Considering the diffusivity of Pt metals, the devices with as-deposited and annealed Pt-based gates were characterized simultaneously and compared with the ones with Ti-based gates. The devices with Ti-based gates yielded superior dc and rf performances to those with Pt-based gates.

In this work, N+-InGaAs/InAlAs recessed gates for InAs/AlSb HFET development are presented. Highly doped N+-InGaAs cap layers are used to decrease the parasitic resistances in contact and access regions. As-grown modulation-doped epitaxy materials exhibit a Hall mobility of 14,200 cm2/V s and a sheet density of 6.15 ×1012 cm−2, while a mobility of 14,600 cm2/V s and a sheet density of 5.61×1012 cm−2 are shown after removal of the N+-InGaAs cap. Benefiting the energy band lowering using the highly doped cap layers, a low contact resistance of 0.06 Ω-mm is achieved. DC performances of I DSS =862mA/mm and g m, peak =927mS/mm and RF performances of f T =24GHz and f max =51GHz are demonstrated in a 2.1μm-gate-length device. An f T -L g product is as high as 51 GH-μm.

Small-bandgap InAs channel materials are potential candidates for high-speed and low-power applications and have been demonstrated in AlSb/InAs/AlSb QWFETs. Taking advantage of their excellent transport properties, we successfully develop an InAs-channel metal-oxide-semiconductor modulation-doped field-effect transistor (MOS-MODFET) using 100-nm PECVD-deposited SiO 2 dielectrics for gate dielectrics. A 2µm-gate-length depletion-mode InAs n-channel MOS-MODFET shows a maximum drain current of 270 mA/mm, a peak transconductance of 189 mS/mm, and a low output conductance of 18 mS/mm in dc characteristics, and a maximum current-gain cut-off frequency of 14.5 GHz and a maximum oscillation frequency of 24.0 GHz in rf performances. The InAs-channel MOS-MODFET presents potentials for further developing complementary circuit devices.

We report the first demonstration of a self-aligned contact technology for III-V MOSFETs. A novel epitaxy process with insitu surface treatment was developed to selectively form a thin continuous germanium-silicon (GeSi) layer on gallium arsenide (GaAs) source and drain (S/D) regions. By precisely and fully converting the GeSi layer into NiGeSi, while diffusing Ge and Si into GaAs to form heavily n+ doped regions, a novel self-aligned nickel germanosilicide (NiGeSi) ohmic contact was achieved. This is expected to significantly enhance the performance of III-V MOSFETs.

We successfully demonstrated DC and RF performance of a metal-oxide-HEMT based on baseline InAs/AlSb HEMT epitaxy material. E-beam evaporated Al 1−x O x was chosen for the dielectric film and its composition characterized by EDS. In a device with 2.0µm gate length, maximum drain current is 286mA/mm and peak transconductance is 495mS/mm at drain voltage of 0.4V. Microwave performance shows a ƒ T of 10 GHz and an ƒ max of 20 GHz. Degraded subthreshold slope but suppressed gate leakage specifically at large electric field were observed.

Conventional InAs/AlSb HEMTs suffer high gate leakage and incomplete pinch-off issues due to instable chemical property of the AlSb and GaSb materials though their excellent performance and circuit application have already been demonstrated. Based on the concerns, we proposed a two-step passivation process for minimizing the negative effect based on developed high-quality InAs/AlSb HEMT materials by solid-source molecular beam epitaxy. Improved device performance is observed.

Growth, fabrication, and characterization for a type II lineup InAs/AlSb HFET are presented. An as-grown epitaxy wafer with a 300 K mobility of 21,300 cm2/V-s and an electron sheet concentration of 1.4times1012 cm-2 was processed into devices. Peak transconductance of 720 mS/mm and drain current of 650 mA/mm at drain voltage of 1.0 V are achieved in a 1-mum gate length device. It is observed strong drain bias dependence of both DC drain currents and transconductances, on-state bell-shaped peaks in the gate leakage, and a large dispersion between DC and RF transconductances. Strong impact ionization along with no hole confinement in the InAs channel are suggested attributions for these phenomena.

We have demonstrated successfully the integration scheme of metallized source/drain extension (M-SDE) with state-of-the-art strained-Si technique. Drain currents of N-FET (Lgate = 40 nm) and P-FET (Lgate = 35 nm) with M-SDE can achieve 1620 muA/mum and 755 muA/mum at |VG-Vt| = |VD| = 1V, respectively. Superior characteristics of junction leakage and source/drain series resistance are also presented. For M-SDE CMOSFETs, the capability of exploiting strain more efficiently is corroborated by the improved stress sensitivity of linear drain current to mechanical stress. M-SDE CMOSFETs exhibit higher stress sensitivity as scaling the gate length.

The concept of diffusion topography engineering (DTE) is proposed and exercised on state-of-the-art 65 nm technology for the first time. Diffusion region extended over STI and therefore resulting in T-shape diffusion profile is created purposely to suppress STI stress and oxide divot. This novel technique delivers up to 33% PMOS and 22% NMOS enhancement, respectively, and results in -10% R.O. speed improvement. When combined with high-stress contact-etch-stop-layer (CESL) , a significant 27% CMOS enhancement is achieved through preferable strain superposition. Both device integrity and reliability are carefully evaluated and neither of them is adversely impacted by DTE.

In this work, we investigate the characteristics of collector current (IC) and breakdown voltage (BVCEO) of SiGe HBTs under the mechanical uniaxial stress by a four-point bending apparatus. DeltaIc and DeltaBVCEO is found to be strain-polarity dependent, and there is a trade-off between DeltaI c and DeltaBVCEO at the same stress condition

Channel backscattering ratios of PMOSFETs with various embedded SiGe source/drain structures are analyzed in terms of the scattering theory. We found that both the backscattering ratio and injection velocity are greatly influenced by the location and recess depth of SiGe source/drain. Although the strain-enhanced injection velocity is beneficial to the current gain, the accompanying backscattering ratio increase adversely impacts the overall performance, and therefore a trade-off exists between injection velocity and backscattering ratio during the optimization of such strain technique. The mechanism of increased backscattering ratio under uniaxial compressive strain is also investigated

The channel backscattering ratios as well as the ballistic efficiency of strained CMOSFETs were studied for both nondegenerate and degenerate-limited cases. We found that the simple nondegenerate assumption can predict strain-induced change of ballistic efficiency with fair accuracy. The mechanism of drain current dependence on strain-induced mobility change was also investigated based on channel backscattering theory.

We report an optimized process-induced strained silicon (PSS) technology for 90nm CMOS generation and beyond. Through the superposition of various PSS techniques, up to 20% performance enhancement is achieved for both N- and PMOS at channel length down to 45nm. The PSS technology exhibits excellent gate oxide breakdown characteristics, isolation characteristics and reliability. A novel spacer-PSS technology is also proposed for the first time and /spl sim/7% enhancement in ring oscillator speed is observed.

The influence of uniaxial process-induced strain on carrier channel backscattering in nanoscale MOSFETs is reported for the first time. It is observed that the backscattering ratio can be reduced by uniaxial tensile strain while it is increased by uniaxial compressive strain mainly due to strain-induced modulation in mean-free-path for backscattering and slight decrease in kBT layer thickness. Nevertheless, both strain polarities improve source-side injection velocity because of reduced carrier effective mass. Impact to current drive under uniaxial strain is analyzed in terms of mean-free-path, kBT layer thickness, ballistic efficiency and injection velocity.

Compressively strained InSb (s-InSb) and Ge (s-Ge) quantum well heterostructures are experimentally studied, with emphasis on understanding and comparing hole transport in these two-dimensional confined heterostructures. Magnetotransport measurements and bandstructure calculations indicate 2.5× lower effective mass for s-InSb compared to s-Ge quantum well at 1.9 × 1012 cm–2. Advantage of strain-induced m* reduction is negated by higher phonon scattering, degrading hole transport at room temperature in s-InSb quantum well compared to s-Ge heterostructure. Consequently, effective injection velocity is superior in s-Ge compared to s-InSb. These results suggest s-Ge quantum well heterostructure is more favorable and promising p-channel candidate compared to s-InSb for future technology node.

A GaAsSb step-graded metamorphic buffer layer is used for growing InAs/AlSb high electron mobility transistor structures on Si substrate by molecular beam epitaxy. The step-graded metamorphic buffer layer effectively reduces the number of microtwins and stacking faults penetrating to the InAs channel as evidenced by transmission electron microscopy. By reducing the planar defects with the metamorphic buffer layer, a significant improvement on electron mobility up to 18 100 cm2/V s and 39 700 cm2/V s at room temperature and 77 K, respectively, is achieved.

The strains in GaAs nanowires, which were grown from 1700- to 80-nm-wide trenches on the Si(001) wafer with SiO2 masks, were investigated by cathodoluminescence. For 1700- to 500-nm-wide trenches, the in-plane tensile strain at 15 K decreases with the decreasing trench width. The strain increases abruptly when the trench width is 300 nm, and then decreases as the trench width is further decreased. The results revealed that the stress induced by the SiO2 sidewalls dominates when the width is less than the depth of the trench. This approach provides an effective technique to measure the strain of a single nanowire and helps for the demonstration of selectively-grown GaAs with a designed strain.

The improved design of sub-micron trenches on Si(001) substrate was demonstrated for defect suppression in semi-polar selectively-grown GaN layers. Cathodoluminescence and transmission electron microscopy measurements revealed a dramatically decreased density of threading dislocations and stacking faults near the surface of the overgrown GaN layer when the trench width ranged from 500 to 1500 nm. It was observed that defects were effectively trapped inside the trench when the ratio of trench depth to the SiO2 thickness is less than 0.66. In addition, a significant reduction of intrinsic polarization electric field was achieved for the InGaN/GaN multiple quantum well on the GaN selectively grown from the Si trenches.

The demonstration of a salicidelike self-aligned contact technology for III-V metal-oxide-semiconductor field-effect transistors (MOSFETs) is reported. A thin and continuous crystalline germanium-silicon (GeSi) layer was selectively formed on n+ doped gallium arsenide (GaAs) regions by epitaxy. A new self-aligned nickel germanosilicide (NiGeSi) Ohmic contact with good morphology was achieved using a two-step annealing process with precise conversion of the GeSi layer into NiGeSi. NiGeSi contact with the contact resistivity (ρc) of 1.57 Ω mm and sheet resistance (Rsh) of 2.8 Ω/◻ was achieved. The NiGeSi-based self-aligned contact technology is promising for future integration in high performance III-V MOSFETs.

We report the characteristics of HfO2/Al2O3/n-InAs metal-oxide-semiconductor capacitors on different reconstructed surface InAs substrates. The HfO2/Al2O3 gate dielectric films deposited on InAs were used to study the interfacial reaction. Compared with (2×4)-surface sample, improvements of capacitance-voltage characteristics for (1×1)-surface sample with lower frequency-dependent capacitance dispersion and higher inversion capacitance are attributed to lower indium composition and less arsenic oxide at Al2O3/InAs interface, as confirmed by x-ray photoelectron spectroscopy. It indicates that the equivalent dangling bond of cations and anions on (1×1)-surface sample tends to avoid the oxidization process and become less pinning.

Ge films were epitaxially grown on GaAs(100) substrates and Ga 0.88 In 0.12 As(100) virtual substrates using an ultrahigh vacuum/ chemical vapor deposition system. The incubation time of Ge growth depends on Ga(In)As surfaces that were processed by different wet chemical solutions. Growth behaviors, such as island growth at the initial stages and selective growth into recessed regions of GaAs, were studied by transmission electron microscopy. To test the quality of Ge grown on GaAs, an n + -Ge/p-GaAs diode was fabricated. We propose that through Ge selective epitaxial growth, Ge can be used as the source-drain of a GaAs metal-oxide-semiconductor field-effect transistor (MOSFET) to overcome some intrinsic limitations of this device.

We investigated the selective growth of germanium into nanoscale trenches on silicon substrates. These nanoscale trenches, the smallest size of which was 50 nm, were fabricated using the state-of-the-art shallow trench isolation technique. The quality of the Ge films was evaluated using transmission electron microscopy. The formation of threading dislocations (TDs) was effectively suppressed when using this deposition technique. For the Ge grown in nanoscale Si areas (e.g., several tens of nanometers), the TDs were probably readily removed during cyclic thermal annealing predominantly because their gliding distance to the SiO 2 sidewalls was very short. Therefore, nanoscale epitaxial growth technology can be used to deposit Ge films on lattice-mismatched Si substrates with a reduced defect density.

We reported the growth of ZnSe nanowires on oxidized Si substrate by molecular-beam epitaxy. It was found that average length, average diameter, and density of the ZnSe nanowires were 1.2 μm, 48 nm, and 1.04 X 10 7 cm -2 , respectively. It was also found that the ZnSe nanowires were structurally uniform and defect-free with a pure zinc blend structure. UV photodetectors were then fabricated by sputtering a thick Au film through an interdigitated shadow mask onto the ZnSe nanowires. It was found that photocurrent to dark current contrast ratio of our ZnSe nanowire photodetector was >90 with 0.1 V applied bias.

This work investigates the impact of different uniaxial strain polarities on channel backscattering in nanoscale complementary metal oxide semiconductor field-effect transistor (CMOSFET). Two carrier statistics, nondegenerate and degenerate-limited, are employed to extract the channel backscattering ratio, ballistic efficiency, and related backscattering factors. While the channel length scales down and the channel stress level increases further, the modulation of channel backscattering ratio, i.e., improved (degraded) by uniaxial tensile (compressive) strain, becomes more prominent. This observation holds true under both carrier statistics, which implies that the nondegenerate case with simple mathematics can be fairly used for evaluation. In addition, the correlation between strain-enhanced mobility gain and drain current improvement is found to be predicted well by the ballistic efficiency deduced with the nondegenerate carrier statistics.