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A 5.6-GHz fractional-N frequency synthesizer with a tunable Gm-C filter is implemented in TSMC CMOS 0.18-μm process. The proposed prototype is with a tunable loop filter bandwidth and hence, the process variations of passive elements of resistance and capacitance can be decreased and the chip area is greatly reduced. Moreover, MASH 1-1-1 sigma–delta (ΣΔ) modulator is adopted for performing the fractional division number and then, improves the phase noise as well. At 1.8-V supply voltage, measured results achieve the locked phase noise of −114.1 dBc/Hz with lower Gm-C bandwidth and −111.7 dBm/C with higher Gm-C bandwidth at 1-MHz offset from carrier of 5.68 GHz. The tuning range from 5.25 to 5.75 GHz, about 500 MHz, corresponding to 9.1% with a tunable voltage of 0–1.8 V, and including pads, the chip area of 0.715 × 0.78 (0.558) mm2. The output power is −8.69 dBm at 5.68 GHz and consumes 56 mW. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2536–2541, 2013

A 21.68 GHz low-power frequency synthesizer with a LC-tank voltage-controlled oscillator (VCO) is implemented in TSMC 90 nm CMOS process.In this proposed circuit, there are three important features. The primary advantage of this circuit is the use of an all-NMOS cross-coupled Colpitts VCO, which decreases transistor parasitic capacitances and reduces phase noise. Second, an injection-locked frequency divider (ILFD) is utilized in the first divider stage to divide the high frequency signal. Third, a low supply voltage of 1.2 V is used to reduce power consumption. Measured results achieve that the locked output frequency is tunable from 21.54–21.96 GHz and the phase noise is about −97.47 dBc/Hz at 1 MHz offset from 21.68 GHz. The mixed output power spectrum at ILFD output frequency of 10.22 GHz is −2.97 dBm and the overall power consumption is 9.24 mW. Including pads, the chip area is 0.8 (0.8 × 1.0) mm2. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:200–205, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27229

A low-chip area and low-phase noise phase-locked loop (PLL) combining fractional-N and integer-N modes operating at 2.4 GHz band is proposed and fabricated in TSMC 0.18-μm CMOS process.The proposed PLL with a Gm-boosted Colpitts voltage-controlled oscillator improves phase noise and a hybrid design of different divider loops achieves fast lock. At 1.8 V supply voltage, the proposed PLL shows a wide tuning range from 2.14 to 2.36 GHz, corresponding to 9.7%, a phase noise of −119.3 dBc/Hz at an offset frequency of 1 MHz from the carrier frequency of 2.14 GHz, a power consumption of 17.3 mW, and an output power of −15.37 dBm. Including pads, the chip area only occupies 0.588 (0.87 × 0.67) mm2. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:2295–2300, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27082

We have demonstrated that 4,4'-dimethyl 2,2'-bipyridine as ligand for Pd(II) catalysts was very efficient for oxidative Heck-type coupling reaction of arylboronic acids with olefins in DMA or CH 3 CN under atm air at 80 °C. The presence of chelated bipyridine ligand isindispensable to achieve high reaction yields and to suppress the formation of biphenyl as homocoupled byproduct.

Air-stable Pd(II) catalysts with cryptand-22 ligand was easily handled in atm air at room temperature for Suzuki cross-coupling reactions of aryl bromides with arylboronic acids both containing electron-withdrawing and electron-donating groups. Generally, reactions proceeded fast to completion in 2 h to give high product yields. Our Pd(OAc)2/cryptand-22 catalyst is unique, since the reaction solution remained yellow during reaction period and air-stable without formation of Pd black as usually observed for ordinary simple amine ligands.

A 24 GHz phase-locked loop (PLL) with a LC-tank voltage-controlled oscillates (VCO) is implemented in TSMC 90 nm CMOS for FMCW MMW radar and sensor application In this proposed circuit including a cross-coupled Colpitts VCO is adopted to decrease the transistor parasitic capacitance and reduce the phase noise. Second, an injection locked frequency divider (ILFD) is utilized in first divider stage to handle the high frequency signal. Measured results achieve that at supply voltage of 1.2 V, the VCO output frequency is tunable and the synthesizer phase noise is about −97.47 dBc/Hz at 1MHz offset from the carrier frequency. The mixed output power spectrum is −2.97 dBm at 10.2 GHz and the power consumption is 9.24 mW.

A new fully integrated, low power complementary cross-coupled quadrature voltage-controlled oscillator (QVCO), divide-by-two frequency divider and double-balance mixer for biomedical applications are presented. The features of our proposed circuit are using charge recycling technique to reduce current from the divider, employing adaptive body-biasing technique (ABB) to drop the minimum voltage clearance of the VCO and achieving two quadrature frequencies which are 2.0 GHz and 4.0 GHz bands. The VCO use differentially tuned MOS varactors can diminish the bad effect of high varactor sensitivity by excluding the common-mode noise. The proposed QVCO and double-balance mixer were implemented in 0.18 um CMOS process with 1.8 V supply voltage, is employed to modulate a wireless communication signal for proposed interactive intelligent healthcare monitoring system (IIHMS). Measured results indicate the divider output frequency is tunable from 1.91 GHz to 2.07 GHz and the QVCO output is from 3.82 GHz to 4.14 GHz, corresponding to 8.05 %. The phase noise of the QVCO operating at 2.02 GHz is −121.8 dBc/Hz at 1 MHz offset. This QVCO draws 2.61 mA and 4.7 mW power consumption. The output power is −17.15 dBm with a 50-Ω load at the frequency of 2.02 GHz. The broadband CMOS double-balance mixer input return loss is higher than 8.5 dB.

A low-power and area-efficient LC-VCO is designed for 10 GHz application. The proposed VCO circuit applies PMOS cross-coupled pairs LC circuits and implemented in TSMC 0.18-um CMOS process. Measured results achieve tuning range of 9.25 to 9.782 GHz, corresponding to 5.6 %, phase noise of -116 dBc/Hz at 1 MHz offset from 9.78 GHz while the tuned control voltage is adjustable from 0 to 0.9V and output power of -8.92 dBm at 50-ƒC termination. The power consumption of core circuit is 1.54 mW and the chip area including pads is 0.464x0.544 (0.240) mm2.

Air-stable Pd(II) catalysts with cryptand-22 ligand was easily handled in atm air at room temperature for Suzuki cross-coupling reactions of aryl bromides with arylboronic acids both containing electron-withdrawing and electron-donating groups. Generally, reactions proceeded fast to completion in 2 h to give high product yields. Our Pd(OAc)2/cryptand-22 catalyst is unique, since the reaction solution remained yellow during reaction period and air-stable without formation of Pd black as usually observed for ordinary simple amine ligands.

This paper proposes a novel Gm?C loop filter instead of a conventional passive loop filter used in a phase-locked loop. The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence the process variations of passive elements of resistance R and capacitance C can be overcome and the chip area is greatly reduced. Furthermore, the MASH 1-1-1 sigma-delta (??) modulator is adopted for performing the fractional division number and hence improves the phase noise as well. Measured results show that the locked phase noise is ?114.1 dBc/Hz with lower Gm?C bandwidth and ?111.7 dBm/C with higher Gm?C bandwidth at 1 MHz offset from carrier of 5.68 GHz. Including pads and built-in Gm?C filter, the chip area of the proposed frequency synthesizer is 1.06 mm2. The output power is ?8.69 dBm at 5.68 GHz and consumes 56 mW with an off-chip buffer from 1.8-V supply voltage.