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Coxsackievirus (CV)-B5 is a common human enterovirus reported worldwide; swine vesicular disease virus (SVDV) is a porcine variant of CV-B5. To clarify the transmission dynamics and molecular basis of host switching between CV-B5 and SVDV, we analysed and compared the VP1 and partial 3Dpol gene regions of these two viruses. Spatiotemporal dynamics of viral transmission were estimated using a Bayesian statistical inference framework. The detected selection events were used to analyse the key molecules associated with host switching. Analyses of VP1 sequences revealed six CV-B5 genotypes (A1–A4 and B1–B2) and three SVDV genotypes (I–III). Analyses of partial 3Dpol revealed five clusters (A–E). The genotypes evolved sequentially over different periods, albeit with some overlap. The major hub of CV-B5 transmission was in China whereas the major hubs of SVDV transmission were in Italy. Network analysis based on deduced amino acid sequences showed a diverse extension of the VP1 structural protein, whereas most sequences were clustered into two haplotypes in the partial 3Dpol region. Residue 178 of VP1 showed four epistatic interactions with residues known to play essential roles in viral host tropism, cell entry, and viral decoating.

A reconfigurable message-passing network is proposed to facilitate message transportation in decoding multimode quasi-cyclic low-density parity-check (QC-LDPC) codes. By exploiting the shift-routing network (SRN) features, the decoding messages are routed in parallel to fully support those specific 19 and 3 submatrix sizes defined in IEEE 802.16e and IEEE 802.11n applications with less hardware complexity. A 6.22- mm2 QC-LDPC decoder with SRN is implemented in a 90-nm 1-Poly 9-Metal (1P9M) CMOS process. Postlayout simulation results show that the operation frequency can achieve 300 MHz, which is sufficient to process the 212-Mb/s 2304-bit and 178-Mb/s 1944-bit codeword streams for IEEE 802.16e and IEEE 802.11n systems, respectively.

The min-sum algorithm is the most common method to simplify the belief-propagation algorithm for decoding low-density parity-check (LDPC) codes. However, there exists a performance gap between the min-sum and belief-propagation algorithms due to nonlinear approximation. In this paper, a self-compensation technique using dynamic normalization is thus proposed to improve the approximation accuracy. The proposed scheme scales the min-sum algorithm by a dynamic factor that can be derived theoretically from order statistics. Moreover, applying the proposed technique to several LDPC codes for DVB-S2 system, the average signal-to-noise ratio degradation, which results from approximation inaccuracy and quantization error, is reduced to 0.2 dB. Not only does it enhance the error-correcting capability of the min-sum algorithm, but the proposed self-compensation technique also preserves a modest hardware cost. After realized with 0.13-mum standard cell library, the dynamic normalization requires about 100 additional gates for each check node unit in the min-sum algorithm

Deposition of ruthenium (Ru) was done using chemical vapor deposition with bis(hexafluoroacetylacetonate)dicarbonyl ruthenium (Ru(hfac) 2 (CO) 2 ) as the precursor, at temperatures, T , ranging from 548≤ T ≤623 K. The initial growth behavior on Si (100) surfaces was investigated using atomic force microscopy and X-ray photoelectron spectroscopy. Three-dimensional nucleus growth was observed. For T =573 K and a precursor partial pressure of 1.3×10 −1 Pa, after 5 min deposition, the nuclei density observed on an H-terminated Si surface of 4.7×10 9 cm −2 was about three times that observed on an SiO 2 surface. Kinetic analysis of nucleation showed a lower activation energy on an H-terminated surface (5 kcal/mole) than that on an oxide surface (11 kcal/mol). As predicted by quantum chemical calculations, the much larger dissociation energy of Ru-hfac (241 kcal/mol) than of Ru–CO (57 kcal/mol) suggests that the deposition is mainly controlled by the hfac dissociation step. Moreover, the existence of adsorbed H was demonstrated to facilitate Ru deposition by removing hfac ligands through the formation of volatile H(hfac).

In this paper, a 64-state four-bit soft-decision Viterbi decoder with power saving mechanism for high speed wireless local area network applications is presented. Based on path merging and prediction techniques, a survivor memory unit with hierarchical memory design is proposed to reduce memory access operations. It is found that more than 70% memory access can be reduced by taking advantage of locality. Moreover, a low complexity compare-select-add unit is also presented, leading to save 15% area and 14.3% power dissipation as compared to conventional add-compare-select design. A test chip has been designed and implemented in 0.18-/spl mu/m standard CMOS process. The test results show that 30/spl sim/40% power dissipation can be reduced, and the power efficiency reaches 0.75 mW per Mb/s at 6 Mb/s and 1.26 mW per Mb/s at 54 Mb/s as specified in IEEE 802.11a.

In this work, we base on multi-layered perceptron neural networks with backpropagation algorithm (MLP/BP) to construct soft decision feedback equalizers (DFEs). The proposal is used to recover distorted 16-point quadrature amplitude modulation (16-QAM) signal. For better performance, error control codes (ECC) are applied to enhance the accuracy of the transmitted data. From the simulations, we note that the MLP/BP-based soft DFEs with bit-interleaved TCM can recover severe distorted 16-QAM data as well as suppress intersymbol interference (ISI) and background additive white Gaussian noise (AWGN). As compared with the LMS DFE, the proposed scheme can provide better bit-error-rate (BER) and packet-error-rate (PER) performance.

The multi-mode message passing switch networks for multi-standard QC-LDPC decoder are presented. An enhanced self-routing switch network with only one barrel shifter permutation structure and a shifter-based two-way duplicated switch network are proposed to support 19 and 3 different sub-matrices defined in IEEE 802.16e and IEEE 802.11n. These proposed switch networks can route the decoding message in parallel by different sizes without signal congestion. The enhanced self-routing switch network can switch the messages at different expansion factors with the lowest hardware complexity. Under the condition of a smaller expansion factor, the decoder throughput can be enhanced from the two-way duplicated switch network by increasing the parallelism. In the 130 nm CMOS synthesis result, the proposed enhanced self-routing and the two-way duplicated switch network gate counts are 21.9 k and 37.4 k at 384 MHz operation frequency.

This paper presents a high speed turbo decoder containing 32 MAP decoders with a inter-block permutation interleaver. The proposed butterfly network guarantees contention-free property and promises parallel processing of turbo decoder without performance degradation. In addition, our approach also features a relocated radix-2 x 2 ACS structure to reduce the critical path delay. After manufacturing by 0.13 μm CMOS process, the test results show the energy efficiency is 0.22 nJ/b/iter in the 160 Mb/s data rate.

The ACS computation and the survivor memory are most power critical, consuming about 90% power in the Viterbi decoder. Based on the low power mechanisms, the scarce state transition (SST) technique and the variable truncation length, we present a Viterbi decoder for the MB-OFDM UWB applications. The SST scheme lowers state transition as well as signal switches in the ACS units. Moreover, the decoding with variable truncation length leads to the access reduction in the survivor memory. The experimental results show more than 30% power reduction under high SNRs as compared to those without SST and variable truncation length.

In this paper, a high-speed Max-Log MAP decoder is presented for soft-in and soft-out trellis decoding. The high throughput is achieved with a two-dimensional ACS design on the high-radix trellis structure, resulting in a highly parallel and area-efficient decoder. We further apply the retiming technique to reduce the critical path delay of ACS operation. After 0.13 mum CMOS chip implementation, the decoder occupies 1.96 mm2 area containing 220 K gates. The estimated timing under the 1.08 V supply and the worst case corner shows that the test chip can achieve the maximum 952 MS/s throughput. To our knowledge, the present Max-Log MAP decoder has the highest throughput with the modest hardware cost.

Coded Orthogonal Frequency Division Multiplexing (COFDM) technology has been widely accepted in many communication systems due to both bandwidth efficiency and robustness to channel distortion. This opens a great of opportunities for SoC society to deal with design complexity by exploiting benefits of giga-scale integration. In this paper, we'll first review the general design concept of COFDM systems and then highlight several key issues in SoC realization. Then a system-level design flow by taking into account both performance indices and hardware complexity will be introduced. Several core modules related to COFDM system will also be addressed to see how better solutions can be achieved, especially for wireless applications. Finally two case studies on WLAN and OFDM-UWB will be discussed to demonstrate our proposals as well as to provide some directions for further research.

An application specific digital signal processor for channel coding is presented. The vector operations can improve both the performance of memory accesses and program code density. The special function units and datapaths for channel decoding accelerate the decoding speed and facilitate algorithm implementation. The processor had been fabricated in a 0.18 /spl mu/m CMOS 1P6M technology. The chip size is 7.73 mm/sup 2/ including 18k bits embedded memory, and the power consumption is 141 mW while decoding Reed-Solomon code and convolutional code. In contrast with general purpose processor designs, the results show this chip has at least 50% improvement in code density and 66% data rate enhancement.

In this paper, a dynamic normalization technique is proposed to approximate the nonlinear operation in decoding LDPC codes. The criterion in determining the normalization factor is also presented with theoretical analysis. The proposed method improves the approximation accuracy as well as the error performance of min-sum algorithm. Furthermore, the hardware implementation benefits from a simplified normalization scheme, leading to reductions in complexity and implementation loss.

A DVB-T/H baseband receiver with multi-stage power control, 2D linear channel equalizer, synchronizer, 2/4/8k-point FFT, and Viterbi/RS decoder is implemented in 0.18mum CMOS. At the highest data rate of 31.67Mb/s, it overcomes 70Hz Doppler frequency and consumes 250mW with a die size of 6.9 times 5.8mm2

In this paper, a (1200,720) LDPC decoder based on an irregular parity check matrix is presented. For achieving higher chip density and less critical path delay, the proposed architecture features a data reordering such that only one specific data bus exists between message memories and computational units. Moreover, the LDPC decoder can also process two different codewords concurrently to increase throughput and datapath efficiency. After chip implementation, a 3.33Gb/s data rate is achieved with 8 decoding iterations in the 21.23mm/sup 2/ 0.18/spl mu/m silicon area. The other 0.13/spl mu/m chip with the 10.24mm/sup 2/ core can further reach a 5.92Gb/s data rate under 1.02V supply.

This paper presents the universal architecture for Reed Solomon (RS) error-and-erasure decoder that can accommodate any codeword with different code parameters and finite field definitions. In comparison with other reconfigurable RS decoders, the proposed design, based on the Montgomery multiplication algorithm, can support various finite field degrees, different primitive polynomials, and erasure decoding functions. In addition, the decoder features an on-the-fly finite field inversion table for high speed error evaluation. The area efficient design approach is also presented. Implemented with 1.2V 0.13mum 1P8M technology, this decoder, correcting up to 16 errors, can operate at 300MHz and reach a 2.4Gb/s data rate. The total gate count is about 54K and the core size is 0.36mm2. The average power consumption is 20.2 mW

This paper presents a new channel equalizer for OFDM-based communication systems. The channel equalizer consists of the adaptive estimation of channel frequency response (CFR) and the signal recovery. CFR is obtained by the two-dimensional linear interpolation of pilots from the frequency axis and the time axis. To avoid the noise enhancement in signal recovery, maximum-likelihood sequence estimation (MLSE) is applied to improve 1.5dB in SNR while using Rayleigh fading channel model with 30Hz Doppler frequency shift. As compared to the linear equalizer without feedback, the division free approach provides more accurate signal recovery in circuit implementation.

A low-density parity-check (LDPC) coded OFDM-based UWB baseband transceiver features a semi-regular LDPC CODEC, a parallel pipelined FFT, and a division-free channel equalizer. The chip is implemented in a standard 0.18 /spl mu/m CMOS process and achieves a 480Mbit/s data rate with an energy consumption of 1.2nJ/b.

An universal VLSI architecture for bit-parallel computation in GF(2/sup m/) is presented. The proposed architecture is based on Montgomery multiplication algorithm, which is suitable for multiple class of GF(2/sup m/) with arbitrary field degree m. Due to the highly regular and modular property, our proposed universal architecture can meet VLSI design requirement. After implemented by 0.18/spl mu/m 1P6M process, our universal architecture can work successfully at 125MHz clock rate. For the finite field multiplier, the total gate count is 1.4K for GF(2/sup m/) with any irreducible polynomial of field degree m/spl les/8, whereas the inverse operation can be achieved by the control unit with gate count of 0.3K.

This paper presents a turbo and Viterbi decoder single chip for 3GPP2 standard. The turbo decoding with a maximum block length of 20,730 and Viterbi decoding with various coding rates are implemented to provide maximum 4.52 Mb/s and 5.26 Mb/s data rates respectively. The memory access is reduced by the input caching scheme. And the system complexity is lowered by the efficient interleaver design. This chip is fabricated in a 0.18 /spl mu/m six-metal standard CMOS process, and the measured power dissipation is 83 mW while decoding a 3.1 Mb/s turbo encoded data stream with six iterations for each block.

In this paper, a high-performance and low-cost COFDM baseband processor is presented. With algorithm exploration in channel estimation and phase error tracking, synchronization becomes more robust to enhance system performance. And better design SNR (1.35/spl sim/7.16dB) can be achieved compared to current solutions. Moreover through architectural exploration, the proposed baseband processor designed in 0.18um CMOS process contains only 370K logic gates and 3.3Kbyte memory. Measurement results show that better hardware efficiency and performance enhancement is achieved for high-speed WLAN applications.

In this paper, the multi-level memory system using error control codes has been proposed. As compared with other approaches for 2/sup m/-level memory cells, our proposal features an effective grouping of several q-level memory cells with q>2/sup m/ in order to create parity bits of error control codes. Therefore, the proposed methodology can enhance both the yield and reliability without area penalty for multilevel memory systems. The BCH (72,64) code of correcting single error is presented for 5-level memory cells. In contrast to 2/sup 2/-level memory cells, our proposal can improve yields from 61.58% to 99.92% for 16 Mbit and make the mass production of 1 Gbit memory practicable under the approximated model for StrataFlash/sup TM/. Since our work was motivated from the use of q-level cells in substitution for 2/sup m/-level cells, not only multi-level flash memory, but also multi-level DRAM systems, can both benefit from our proposed methodology.

This paper presents a 166Mb/s, 64-state, radix-4, 16-level soft decision Viterbi decoder for high speed WLAN applications. With the path merging and trace forward techniques, the memory read operations are reduced to save power consumption. A test chip is fabricated in 0.35/spl mu/m IP4M CMOS process, and can achieve the maximum throughput rate of 166Mbit/s under 3.3V. The measured power consumption is below 55mW under 166Mb/s throughput rate at 2.2V.

In this paper, a low-power Reed-Solomon (RS) decoder for STM-16 optical communications is presented. It mainly contains one (255,239) RS decoder and four 2 K-bit embedded memory for correcting the received codewords. Except the novel syndrome calculator reducing half the syndrome computations, our proposal also features a modified Berlekamp-Massey algorithm in the key equation solver and a terminated mechanism in the Chien search circuit. The (255,239) RS decoder is implemented by 0.25 /spl mu/m CMOS 1P5M standard cells with gate counts of 32.9 K and area of 2.03 mm/sup 2/. Simulation results show our approach can work successfully at the data rate of 2.5-Gbps and achieve 80% reduction of power dissipation on the average.