24 results on '"Chew, Soon Aik"'
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2. Cu pad surface height evaluation technique by in-line SEM for wafer hybrid bonding
3. The Challenges and Solutions of Cu/SiCN Wafer-to-Wafer Hybrid Bonding Scaling Down to 400nm Pitch
4. Cu pad surface height evaluation technique by in-line SEM for wafer hybrid bonding
5. 700nm pitch Cu/SiCN wafer-to-wafer hybrid bonding
6. Reliability Investigation of W2W Hybrid Bonding Interface: Breakdown Voltage and Leakage Mechanism
7. Titanium (germano-)silicides featuring 10−9 Ω·cm2 contact resistivity and improved compatibility to advanced CMOS technology
8. (Invited) Gate-All-Around Transistors Based on Vertically Stacked Si Nanowires
9. Titanium Silicide on Si:P With Precontact Amorphization Implantation Treatment: Contact Resistivity Approaching $1 \times 10^{-9}$ Ohm-cm2
10. Optimization of standard As ion implantation for NMOS Si bulk FinFETs extension
11. Diffusion and Gate Replacement: A New Gate-First High- $k$ /Metal Gate CMOS Integration Scheme Suppressing Gate Height Asymmetry
12. Process Optimization of p+LDD in 130nm Process Technology using TCAD Simulation
13. TCAD Simulation of Local Mechanical Stress Reduction by Use of a Compressive Silicon Nitride/Silicon Oxynitride Etch Stop Bi-Layer for CMOS Performance Enhancement
14. Dummy design characterization for STI CMP with fixed abrasive
15. Thermal and plasma treatments for improved (sub-)1 nm equivalent oxide thickness planar and FinFET-based replacement metal gate high-k last devices and enabling a simplified scalable CMOS integration scheme
16. Effective Work Function Engineering for Aggressively Scaled Planar and Multi-Gate Fin Field-Effect Transistor-Based Devices with High-k Last Replacement Metal Gate Technology
17. W versus Co–Al as Gate Fill-Metal for Aggressively Scaled Replacement High-k/Metal Gate Devices for (Sub-)22 nm Technology Nodes
18. Titanium Silicide on Si:P With Precontact Amorphization Implantation Treatment: Contact Resistivity Approaching 1 \times 10^-9 Ohm-cm2.
19. Implementing cubic-phase HfO2 with κ-value ∼ 30 in low-VT replacement gate pMOS devices for improved EOT-Scaling and reliability
20. TCAD Simulation of Local Mechanical Stress Reduction by Use of a Compressive Silicon Nitride/Silicon Oxynitride Etch Stop Bi-Layer for CMOS Performance Enhancement.
21. A Low-Power HKMG CMOS Platform Compatible With Dram Node 2× and Beyond.
22. Effective Work Function Engineering for Aggressively Scaled Planar and Multi-Gate Fin Field-Effect Transistor-Based Devices with High-$k$ Last Replacement Metal Gate Technology
23. W versus Co--Al as Gate Fill-Metal for Aggressively Scaled Replacement High-$k$/Metal Gate Devices for (Sub-)22 nm Technology Nodes
24. Integration Challenges and Options of Replacement High-κ/Metal Gate Technology for (Sub-)22nm Technology Nodes
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