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Contact engineering of two-dimensional semiconductors is a central issue for performance improvement of micro-/nanodevices based on these materials. Unfortunately, the various methods proposed to improve the Schottky barrier height normally require the use of high temperatures, chemical dopants, or complex processes. This work demonstrates that diffused electron beam energy (DEBE) treatment can simultaneously reduce the Schottky barrier height and enable the direct writing of electrical circuitry on van der Waals semiconductors. The electron beam energy projected into the region outside the electrode diffuses into the main channel, producing selective-area n-type doping in a layered MoTe

This study enhances the reliability of via-contact type amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) with optimal contact capping area under negative bias illumination stress (NBIS). The $\text{I}_{\text {D}}$ - $\text{V}_{\text {G}}$ transfer curves for source and drain electrodes with no capping area exhibited a larger negative threshold voltage ( $\text{V}_{\text {TH}}$ ) shift after NBIS. Similarly, the drain electrode with capping area also shows serious electrical degradation. Compared to these two electrode types, however, a source electrode with capping area exhibited excellent stability after NBIS due to the lack of holes injecting into the gate oxide near source side. This optimal contact capping area provides a novel device structure which improves NBIS reliability. Finally, this work utilizes the SILVACO technology computer-aided design (TCAD) simulation to demonstrate the changes in the energy band and electron field distribution after NBIS for different capping metal structures. Then the hole injection and electrical degradation mechanisms are verified.

This work investigates the influence of a supercritical fluid (SCF) treatment on the characteristics of resistive random access memory. A comparison between the experimental results for the device at initial, after the overset process, and after the SCF treatment, shows that the treatment dopes oxygen ions and generates defects in the switching region (SR). Moreover, the changes in the ratio of the components of the SR after the SCF treatment improve memory characteristics, including a lower set/reset voltage (V SET/V RESET), and higher resistances at low resistance state and high resistance state.

This study examines self-heating-related instability in n-channel low-temperature polysilicon thin-film transistors with different source/drain contact hole densities. Devices with more contact holes exhibit a higher on-current without additional parasitic capacitance, further enhancing the RC delay property. For high-current-induced self-heating stress, a device with one contact hole has one hump due to the kink effect. However, a device with six contact holes has two humps, induced by the kink effect and thermionic field emission. COMSOL simulations of heat distribution and energy bands are performed to examine the different degradation behaviors, and then physical models are proposed.

The oxygen (O

Precisely controllable and reversible p/n-type electronic doping of molybdenum ditelluride (MoTe

In the investigation of the reliability of a back-channel-etching type amorphous InGaZnO thin film transistor, we found that hot carrier stress has caused an abnormal parallel negative threshold voltage shift in the I D–V G measurement. An electrical measurement method named drain stress was established to investigate this instability. Through the analysis of recovery behavior, gate bias stress and Silvaco simulation, we confirmed that holes from the drain side inject into the passivation layer and/or back-channel interface region rather than into the gate insulator under the transverse electric field. A physical model is proposed to verify this electrical degradation behavior. This work demonstrates that drain stress is valuable in examining the quality of the passivation layer in thin film transistors.

ReRAM is a promising next-generation nonvolatile memory (NVM) with fast write speed and low-power operation. However, ReRAM faces two major challenges in read operations: 1) low read yield due to wide resistance distribution and 2) the requirement of accurate bit line (BL) bias voltage control to prevent read disturbance. This study proposes two process-variation-tolerant schemes for current-mode read operation of ReRAM: parallel-series reference-cell (PSRC) and process-temperature-aware dynamic BL-bias (PTADB) schemes. These schemes are meant to improve the read speed and yield of ReRAM, while taking read disturbance into consideration. PSRC narrows the reference current distribution to achieve high read yield against resistance variation. PTADB achieves small fluctuations in BL bias voltage to prevent read disturbance, while providing rapid BL precharge speeds. This study fabricated a 4-Mb ReRAM macro to confirm the effectiveness of the proposed schemes for both SLC and MLC operations. The fastest sub-8-ns (7.2 ns) read-write random access time among megabit scaled embedded NVM macros has been demonstrated.

In this paper, theoretical and experimental analyses have been performed to explore the electrothermal characteristics in low-temperature polycrystalline-silicon thin-film transistors (LTPS TFTs). A theoretical simulation reveals that electrothermal effects strongly influence the performance of LTPS TFTs, particularly under high-current conditions. Measurements show that, under extremely high currents, LTPS devices demonstrate an open-circuit behavior, while the behavior of devices based on single-crystalline silicon films using an SOI CMOS process results in a short-circuit model. In summary, both the simulation and measurements indicate that grain boundaries will degrade the electrothermal properties of the LTPS thin film and suppress reliability in TFT design.

In this study, we investigate the hot-carrier stress effects on the high-frequency and RF power characteristics of Si/SiGe hetero-junction bipolar transistors (HBTs). By simultaneously applying a high collector current density and a high collector–base voltage on Si/SiGe HBTs, because hot carriers will be induced; they will then degrade device performance. This is interesting because this stress condition is similar to the DC bias condition of a current source RF power amplifier, termed as the "mixed-mode" stress. We find that not only the high-frequency characteristic is adversely affected by but also the output power performance of Si/SiGe HBTs suffers from this electrical stress. In addition, we found that the degradations of the high-frequency and power characteristics of such HBTs are worse in constant-base-current measurement than in constant-collector-current measurement. We finally examined the degradations in terms of parasitic resistance and the ideality factors of base and collector currents using a large-signal model.

A new enhanced displacement-current triggering by adding floating P+ diffusions at each source finger edge for the HV LDNMOSFET is proposed. Unlike the conventional substrate-triggered ESD protection technologies, it is very easy to implement the scheme by the layout without any special circuit and additional component. With a total width of 1600 μm, the HBM/ MM ESD performance improvements from 1.5 kV/ 150 V to 5.5 kV/ 450 V are achieved.

From the experimental measurements, the dominant charge source for a packaged IC chip during a charged-device model (CDM) ESD event is the capacitor between the die-attach plate and the metal bus line, C SUB . By adding a bonding wire between the die-attach plate and the Vss pin, a parallel inductor to the C SUB can be created. The CDM-robustness for the packaged IC chip is significantly improved because of this parallel LC resonance circuit.

Nanometer-sized Schottky diodes based on nickel monosilicide (NiSi)/silicon nanowire (SiNW) heterojunction have been fabricated and studied for their electrical transport characteristics. The SiNW was fabricated by scanning probe lithography (SPL) and tetramethylammonium (TMAH) wet etching. The diameter and height of the SiNWs were 60 and 25 nm, respectively. A Schottky barrier diode was obtained by patterning nickel film onto half of the SiNW by conventional lithography, and then forming nickel monosilicide by the solid state reaction between nickel and silicon under rapid thermal annealing (RTA) in N2 ambient for 1 min. The current–voltage characteristics measured exhibited clear rectifying behavior consistent with a 0.22 eV schottky barrier height, and no reverse bias breakdown was observed up to a voltage of -5 V.

A DC and pulse stress electro-thermal model that can well describe the dynamic thermal behaviors of most interconnections fabricated in CMOS technology is derived and demonstrated. This model provides for the first time a simple methodology to evaluate the time dependent temperature and resistance of the interconnection under an applied voltage stress, especially critical to E-Fuse development.

In this paper, we present an ultra high density 3D Via RRAM with 28nm HKMG CMOS fully compatible process. It is the first time to report a cross-point 3D RRAM formed by the stacked 30nm × 30nm Cu Via and Cu metal line of 28nm HKMG CMOS Cu single damascene process. The 3D Via RRAM cell consists of a TaON-based resistive film, Cu Via as top electrode, and Cu metal as bottom electrode. The TaON-based RRAM film is a composite layer of backend metal glue layer of Ta and TaN in 28nm Cu damascene process. Moreover, in the compact 3D Via RRAM structure, the unit area of a single stacked cell-string is reduced to only 4 times of Via size by 28nm CMOS design rules. Since the cross-point 3D Via RRAM is fabricated without extra TMO film or process step, this excellent cell scalability and compatibility can provide a competitive low cost and high density embedded NVM solution in advanced CMOS logic nodes.

High contact resistance between TMDs and metals has been identified as an outstanding issue. TMDs tend to form a substantial Schottky barrier (SB) with commonly used metals. Air-stable graphene electrodes stacked on the WSe2 by transfer technique have been reported. However, unipolar conduction has not been achieved in FETs based on TMD materials and graphene electrodes. Here we report a synthetic process to directly grow WSe2 monolayers along the edge of patterned few-layered graphene, forming the lateral heterojunction between the graphene and monolayer WSe2. The few-layered WSe2 bridges the few-layer graphene and monolayer WSe2, and an interpenetrating layered structure is formed between graphene and WSe2. As a result, the WSe2 monolayer channel and the junction to the graphene can be formed at the same time by the synthesis method, where graphene serves as source and drain. Graphene is in-situ heavily p-doped by H2 with covent bond during WSe2 growing process. Such a unique junction structure leads to a barrier less ohmic contact between doped graphene and WSe2. Unipolar WSe2 PFET with laterally contacted p-doped graphene source/drain (p-G/WSe2 PFET) can be achieved for the first time. With Pd contacted source/drain metal, the unipolar PFET perform Ion/Ioff > 105 and field effect mobility ~20 cm2/Vˑs. Moreover we can still have unipolar PFET with Ti source/drain metal exceeds 103 Ion/Ioff ratio even Ti work function is low (4.3 eV) and close to the conduction band edge of WSe2 (electron affinity of WSe2~ 4.03 eV).

Nonvolatile memory has become a bottleneck in attempts to reduce the energy consumption of electronic systems. Several emerging forms of nonvolatile memory have shown promise in overcoming these difficulties, achieving faster write speeds and lower power operations than those afforded by Flash memories. Unfortunately, constraints related to bitline bias-voltage, small read cell current, and process variation detract considerably from the efficiency of read operations. This paper provides a review of the challenges and trends associated with the read sensing circuitry used in emerging nonvolatile memories.

Compared with the Ni/HfO X device, the Ni/AlO X /HfO X unipolar device exhibits a higher R HIGH and the robust endurance of 10k cycles without any soft-errors. A possible mechanism with filament model is proposed to describe these results. The high operation speed of 40 ns, low operation current possibly down to 10 µA, and stable nonvolatile characteristic at 85 °C in the Ni/AlO X /HfO X device are demonstrated to realize the device to be the next generation nonvolatile memory.

The binary oxide based resistive memories showing superior electrical performances on the resistive switching are reviewed in this paper. The status and challenges of the HfO X based resistive device with excellent memory properties are presented. Several future challenges for the filamentary type switching device are also addressed.

Several emerging nonvolatile memories (NVMs) including phase-change RAM (PCRAM) [1–3], MRAM [4–5], and resistive RAM (RRAM) [6–8] have achieved faster operating speeds than embedded Flash. Among those emerging NVMs, RRAM has advantages in faster write time, a larger resistance-ratio (R-ratio), and smaller write power consumption. However, RRAM cells have large cross-die and within-die resistance variations (R-variations) and require low read-mode bitline (BL) bias voltage (V BL-R ) to prevent read disturbance. This work proposes process/resistance variation-insensitive read schemes for embedded RRAM to achieve fast read speeds with high yields. An embedded mega-bit scale (4Mb), single-level-cell (SLC) RRAM macro with sub-8ns read-write random-access time is presented. Multi-level-cell (MLC) operation with 160ns write-ver-ify operation is demonstrated.

The memory performances of the HfO X based bipolar resistive memory, including switching speed and memory reliability, are greatly improved in this work. Record high switching speed down to 300 ps is achieved. The cycling test shed a clear light on the wearing behavior of resistance states, and the correlation between over-RESET phenomenon and the worn low resistance state in the devices is discussed. The modified bottom electrode is proposed for the memory device to maintain the memory window and to endure resistive switching up to 1010 cycles.

Although a significant effort was made recently in the development of binary oxide based resistive memory (RRAM) [1,2], reliability issue is still the most concern, but less addressed [3,4]. By stressing the device in high resistance state (HRS) with constant voltage of the same bias polarity during SET process, the disturbed time is found to exhibit extreme low Weibull slope (~0.3). This characteristic can drastically shrink the reliability margin for reading process [4]. Inserting a thin Al 2 O 3 between the transition metal oxide and bottom electrode was proposed previously to improve read disturb immunity at room temperature [4]. However, the effect of high temperature (125°C) on the read disturb of this stacked layer (HfOx/Al 2 O 3 ) has not yet been studied.

A 30×30 nm2 HfO x resistance random access memory (RRAM) with excellent electrical performances is demonstrated for the scaling feasibility in this work. A 1 Kb one transistor and one resistor (1T1R) array with robust characteristics was also fabricated successfully. The device yield of the 1 Kb array is 100%, and the endurance for these devices can exceed 106 cycles by a pulse width of 40 ns. Two effective verification methods, which make a tight distribution of high resistance (R HIGH ) and low resistance (R LOW ) are proposed for the array to ensure a good operation window. A thin AlO x buffer layer under the HfO x layer was adopted to enhance the read disturb immunity. Without large parasitic capacitance, the 1T1R RRAM devices exhibit excellent program(PGM)/erase(ERS) disturb immunity.

A novel HfO2-based resistive memory with the TiN electrodes is proposed and fully integrated with 0.18 mum CMOS technology. By using a thin Ti layer as the reactive buffer layer into the anodic side of capacitor-like memory cell, excellent memory performances, such as low operation current (down to 25 muA), high on/off resistance ratio (above 1,000), fast switching speed (5 ns), satisfactory switching endurance (>106 cycles), and reliable data retention (10 years extrapolation at 200degC) have been demonstrated in our memory device. Moreover, the benefits of high yield, robust memory performance at high temperature (200degC), excellent scalability, and multi-level operation promise its application in the next generation nonvolatile memory.

Local oxidation (LOCOS) fin field-effect transistors (finFETs), a type of delta-FETs, are studied here for comparison with silicon-on-insulator (SOI) finFETs and bulk silicon finFETs. In our simulation, the LOCOS finFET shows a lower leakage current than the bulk finFET and a driving capability superior to that of the SOI finFET. The results can be attributed to the partial connection between the channel region and the substrate in LOCOS finFETs. The partially isolated oxide layer of LOCOS provides electrical isolation to suppress leakage, and the interspace between isolated oxide layers provides good thermal conduction to sustain a high driving current. For device fabrication, different parameters, fin height (H), gate length (L), and oxide interspace (S), are also investigated. The results show that the LOCOS finFET structure is an exceptional alternative for nanodevice applications.

In this paper, a physical mechanism is proposed where the holding voltage of the semiconductor-controlled rectifier (SCR) is predominated by the accumulation of minority carriers. Two-dimensional simulation is used to demonstrate this mechanism where the carrier distribution of SCR devices is calculated and analyzed. It has been clearly proven that the distribution of minority carriers highly correlates to holding voltage. Accordingly, a layout approach has also been designed and experiments have confirmed that an increment in holding voltage can be performed. It can be concluded that the optimization of the topological structure will markedly increase holding voltage and eventually prevent the complementary metal–oxide–semiconductor (CMOS) integration circuit from minimizing the latch-up effect. Moreover, because of its high current capabilities, the optimized SCR can be used as an ideal candidate for electrostatic discharge protection (ESD) applications.

The infrared spectrum of solid and liquid hydrogen was recorded using a Fourier spectrometer. The pure rotational U transitions, U 0 (0) in solid para hydrogen and U 0 (1) in solid normal hydrogen, with the accompanying phonon branches were observed for the first time. In addition, the rotational double transitions S 0 (0) + S 0 (1) and S 0 (1) + S 0 (1) were identified. The identifications of these transitions are based on positions calculated by making use of gas phase molecular constants. In the liquid the double transitions are preserved but the single transitions U 0 (0) and U 0 (1) are entirely absent. The region of Q 1←0 ( J ) reveals structure which has not been reported before. Its interpretation is presented.