107 results on '"Chen, Pai-Yu"'
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2. Review of physics-based compact models for emerging nonvolatile memories
3. Cross-point memory design challenges and survey of selector device characteristics
4. Impact of Nonideal Resistive Synaptic Device Behaviors on Implementation of Sparse Coding Algorithm
5. Peripheral Circuit Design Considerations of Neuro-inspired Architectures
6. Technological Benchmark of Analog Synaptic Devices for Neuroinspired Architectures
7. Device and materials requirements for neuromorphic computing
8. NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning
9. X-Point PUF: Exploiting Sneak Paths for a Strong Physical Unclonable Function Design
10. Understanding the resistive switching characteristics and mechanism in active SiOx-based resistive switching memory.
11. A ferroelectric field effect transistor based synaptic weight cell
12. Reliability perspective of resistive synaptic devices on the neuromorphic system performance
13. A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors
14. Fully parallel RRAM synaptic array for implementing binary neural network with (+1, −1) weights and (+1, 0) neurons
15. Random sparse adaptation for accurate inference with inaccurate multi-level RRAM arrays
16. Ferroelectric FET analog synapse for acceleration of deep neural network training
17. NeuroSim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures
18. System-level benchmark of synaptic device characteristics for neuro-inspired computing
19. NbOx based oscillation neuron for neuromorphic computing
20. Design of Ternary Neural Network With 3-D Vertical RRAM Array
21. A Multilayer Approach to Designing Energy-Efficient and Reliable ReRAM Cross-Point Array System
22. Design and optimization of a strong PUF exploiting sneak paths in resistive cross-point array
23. Quasi-Analytical Model of 3-D Vertical-RRAM Array Architecture for MB-Level Design
24. Exploiting NbOx metal-insulator-transition device as oscillation neuron for neuro-inspired computing
25. Energy-Efficient Adaptive Computing With Multifunctional Memory
26. MNSIM: Simulation Platform for Memristor-based Neuromorphic Computing System
27. Binary neural network with 16 Mb RRAM macro chip for classification and online training
28. Design Tradeoffs of Vertical RRAM-Based 3-D Cross-Point Array
29. Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing
30. Weight tuning of resistive memories and convolution kernel operation on cross-point array for neuro-inspired computing
31. Design of Resistive Synaptic Array for Implementing On-Chip Sparse Learning
32. Physical Unclonable Function Exploiting Sneak Paths in Resistive Cross-point Array
33. Demonstration of Convolution Kernel Operation on Resistive Cross-Point Array
34. Security Primitive Design with Nanoscale Devices
35. Design of a reliable RRAM-based PUF for compact hardware security primitives
36. Hardware-efficient learning with feedforward inhibition
37. Partition SRAM and RRAM based synaptic arrays for neuro-inspired computing
38. MNSIM: Simulation Platform for Memristor-based Neuromorphic Computing System
39. Emerging Memory Technologies: Recent Trends and Prospects
40. Compact Modeling of RRAM Devices and Its Applications in 1T1R and 1S1R Array Design
41. Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect
42. Programming Protocol Optimization for Analog Weight Tuning in Resistive Memories
43. On-Chip Sparse Learning Acceleration With CMOS and Resistive Synaptic Devices
44. Mitigating effects of non-ideal synaptic device characteristics for on-chip learning
45. Fully parallel write/read in resistive synaptic array for accelerating on-chip learning
46. MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System.
47. Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration
48. Exploiting resistive cross-point array for compact design of physical unclonable function
49. Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design
50. Electroforming and resistive switching in silicon dioxide resistive memory devices
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