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In previous SRAM designs, reducing minimum operating voltage (VDDmin) inevitably resulted in devices with a large cell area (A). This work proposes an L-shaped 7T cell (L7T) and read-bitline (RBL) swing expansion scheme (RBL-EXPD) to minimize A\astVDDmin for low-voltage applications. This L7T features an area-efficient cell layout and a read-disturb free decoupled 1T read port (RP) capable of providing a wide space for write margin improvement. The RBL-EXPD employs (1) boosted RBL (BRBL), (2) 1T-RP with asymmetric-VTH, (AV-1TRP) and (3) offset cell-VDD biasing (OFS-CVDD) to expand RBL swing in both the upward and downward directions securing both ‘High’ and ‘Low’ sensing margins. A 65 nm 256-row 32 Kb L7T SRAM macro-fabricated using BRBL and AVTH-RP achieved a 260 mV VDDmin. The resulting A\astVDDmin is ~50% lower than that of conventional 8T SRAM devices. [ABSTRACT FROM AUTHOR]

TSV-based 3D die-stacking technology enables the reuse of pre-designed, pre-tested logic dies stacked with multiple memory layers (NSTACK) in various configurations to form a universal-memory-capacity platform (UMCP). However, conventional 3D memories suffer speed, power and yield overheads due to the large parasitic load of TSV and cross-layer PVT variations when implemented in large NSTACK with wide IO, especially using via-last TSVs. This work proposes a semi-master-slave (SMS) memory structure with self-timed differential-TSV signal transfer (STDT) scheme to improve the speed, power, and yield of 3D memory devices, while providing high scalability in NSTACK for 3D-UMCP. The SMS scheme achieves the following: 1) a constant-load logic-SRAM interface across various NSTACK; 2) high tolerance for variations in cross-layer PVT, and 3) at-speed pre-bonding KGD sorting. The STDT scheme employs a TSV-load tracking scheme to achieve small TSV voltage swing for suppressing power and speed overheads of cross-layer TSV signal communication resulting from large TSV parasitic loads, particularly in UMCP designs with scalable NSTACK and wide-IO. To verify the viability of the proposed structure and scheme, we developed a 2-layer 32 kb 3D-SRAM testchip with layer-scalable test-modes using a via-last TSV process with die-to-die bonding. This testchip confirmed the functionality and demonstrated superior scalability in NSTACK with small speed overheads. [ABSTRACT FROM AUTHOR]

Density-prioritized memories such as NAND-ROM require a longer single-ended bitline (BL) sensing scheme to maintain high cell array efficiency and therefore suffer from a reduced BL sensing margin at ultra-low supply voltages (VDD) for read-0. This is the result of 1) reduced BL discharge driving current due to limited cell size and driving voltage; and 2) a larger BL false drop noise for read-1. This study proposes a data-aware sensing reference (DASR) scheme, capable of maintaining sensing margins for both read-0 and read-1 under given timing constraints. The key mechanism involved in maintaining the sensing margin is the adaptive changing of the reference voltage (VREF), such that the sensing headroom or potential range (VBL-VREF) for read-1 and read-0 overlap, as in differential BL sensing. Two 256 Kb DASR NAND-ROM macros, with and without code-inversion schemes, were fabricated using a 90 nm bulk CMOS logic process. The 256 Kb DASR NAND-ROM macros are functional down to 0.25 V. DASR also increases the access speed by 66.7% at 0.31 V VDD, compared with the conventional approach without the proposed DASR scheme. [ABSTRACT FROM AUTHOR]