120 results on '"Chen, Jwu E."'
Search Results
2. Using the Test Guardband Estimation Method to Forecast Future Semiconductor Yield Trends
3. Retesting Schemes That Improve Test Quality and Yield Using a Test Guardband
4. A Practical Approach to the Curriculum of Statistics for Engineering Students.
5. Repeated Testing Applications for Improving the IC Test Quality to Achieve Zero Defect Product Requirements
6. Recycling Test Methods to Improve Test Capacity and Increase Chip Shipments
7. Prediction of the Test Yield of Future Integrated Circuits Through the Deductive Estimation Method
8. Development of an Emotional Robot as a Teaching Assistant
9. Application of Three-Repetition Tests Scheme to Improve Integrated Circuits Test Quality to Near-Zero Defect
10. Wafer Defect Pattern Labeling and Recognition Using Semi-Supervised Learning
11. Wafer Scratch Pattern Reconstruction for High Diagnosis Accuracy and Yield Optimization
12. Using Enhanced Test Systems Based on Digital IC Test Model for the Improvement of Test Yield
13. Unbalanced-Tests to the Improvement of Yield and Quality
14. Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling
15. Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering
16. Machine Learning-Based Detection Method for Wafer Test Induced Defects
17. Hidden Wafer Scratch Defects Projection for Diagnosis and Quality Enhancement
18. IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection
19. Structural Fault Based Specification Reduction for Testing Analog Circuits
20. Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing
21. Fault Diagnosis for Linear Analog Circuits
22. Oscillation Ring Delay Test for High Performance Microprocessors
23. Development of an Emotional Robot as a Teaching Assistant
24. The Decision Mechanism Uses the Multiple-Tests Scheme to Improve Test Yield in IC Testing
25. Innovative Practice on Wafer Test Innovations
26. Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis
27. Test yield and quality analysis models of chips
28. Identifying invalid states for sequential circuit test generation
29. Design of a range-segmented CMOS current-mode exponential circuit
30. Modelling and optimisation algorithm for length‐matching escape routing of differential pairs
31. Checkpoints in irredundant two-level combinational circuits
32. PACES: A Partition-Centering-Based Symmetry Placement for Binary-Weighted Unit Capacitor Arrays
33. Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCs
34. Optimal common-centroid-based unit capacitor placements for yield enhancement of switched-capacitor circuits
35. Generic Reliability Analysis for Safety-Critical FlexRay Drive-By-Wire Systems
36. A Novel Fractional Discrete Cosine Transform Based Reversible Watermarking for Biomedical Image Applications
37. Multi-point correction method in CMOS current-mode function design
38. CMOS current-mode hyperbolic tangent sigmoid function implementation using multi-segment approximations
39. A CMOS Current-Mode S-Shape Correction Circuit with Shape-Adjustable Control
40. Histogram Modification and Wavelet Transform for High Performance Watermarking
41. A Novel Fractional-Discrete-Cosine-Transform-Based Reversible Watermarking for Healthcare Information Management Systems
42. Nested Quantization Index Modulation for Reversible Watermarking and Its Application to Healthcare Information Management Systems
43. Optimization and Implementation of Scaling-Free CORDIC-Based Direct Digital Frequency Synthesizer for Body Care Area Network Systems
44. Haar-Wavelet-Based Just Noticeable Distortion Model for Transparent Watermark
45. A Unified Algorithm for Subband-Based Discrete Cosine Transform
46. Difference-Equation-Based Digital Frequency Synthesizer
47. Yield-award placement optimization for Switched-Capacitor analog integrated circuits
48. Design Methodology for Yield Enhancement of Switched-Capacitor Analog Integrated Circuits
49. Robustness analysis of the FlexRay system through fault tree analysis
50. Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated Circuits
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.