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Facts extraction is pivotal for constructing knowledge graphs. Recently, the increasing demand for temporal facts in downstream tasks has led to the emergence of the task of temporal fact extraction. In this paper, we specifically address the extraction of temporal facts from natural language text. Previous studies fail to handle the challenge of establishing time-to-fact correspondences in complex sentences. To overcome this hurdle, we propose a timeline-based sentence decomposition strategy using large language models (LLMs) with in-context learning, ensuring a fine-grained understanding of the timeline associated with various facts. In addition, we evaluate the performance of LLMs for direct temporal fact extraction and get unsatisfactory results. To this end, we introduce TSDRE, a method that incorporates the decomposition capabilities of LLMs into the traditional fine-tuning of smaller pre-trained language models (PLMs). To support the evaluation, we construct ComplexTRED, a complex temporal fact extraction dataset. Our experiments show that TSDRE achieves state-of-the-art results on both HyperRED-Temporal and ComplexTRED datasets., Comment: Accepted to ACL2024 main conference

Temporal facts, which are used to describe events that occur during specific time periods, have become a topic of increased interest in the field of knowledge graph (KG) research. In terms of quality management, the introduction of time restrictions brings new challenges to maintaining the temporal consistency of KGs. Previous studies rely on manually enumerated temporal constraints to detect conflicts, which are labor-intensive and may have granularity issues. To address this problem, we start from the common pattern of temporal facts and propose a pattern-based temporal constraint mining method, PaTeCon. Unlike previous studies, PaTeCon uses graph patterns and statistical information relevant to the given KG to automatically generate temporal constraints, without the need for human experts. In this paper, we illustrate how this method can be optimized to achieve significant speed improvement. We also annotate Wikidata and Freebase to build two new benchmarks for conflict detection. Extensive experiments demonstrate that our pattern-based automatic constraint mining approach is highly effective in generating valuable temporal constraints.

Josephson tunneling in twisted cuprate junctions provides a litmus test for the pairing symmetry, which is fundamental for understanding the microscopic mechanism of high temperature superconductivity. This issue is rekindled by experimental advances in van der Waals stacking and the proposal of an emergent d+id-wave. So far, all experiments have been carried out on Bi$_2$Sr$_2$CaCu$_2$O$_{8+x}$ (Bi-2212) with double CuO$_2$ planes but show controversial results. Here, we investigate junctions made of Bi$_2$Sr$_{2-x}$La$_x$CuO$_{6+y}$ (Bi-2201) with single CuO$_2$ planes. Our on-site cold stacking technique ensures uncompromised crystalline quality and stoichiometry at the interface. Junctions with carefully calibrated twist angles around 45{\deg} show strong Josephson tunneling and conventional temperature dependence. Furthermore, we observe standard Fraunhofer diffraction patterns and integer Fiske steps in a junction with a twist angle of 45.0$\pm$0.2{\deg}. Together, these results pose strong constraints on the d or d+id-wave pairing and suggest an indispensable isotropic pairing component., Comment: 32 pages, 5 figures

Temporal facts, the facts for characterizing events that hold in specific time periods, are attracting rising attention in the knowledge graph (KG) research communities. In terms of quality management, the introduction of time restrictions brings new challenges to maintaining the temporal consistency of KGs and detecting potential temporal conflicts. Previous studies rely on manually enumerated temporal constraints to detect conflicts, which are labor-intensive and may have granularity issues. We start from the common pattern of temporal facts and constraints and propose a pattern-based temporal constraint mining method, PaTeCon. PaTeCon uses automatically determined graph patterns and their relevant statistical information over the given KG instead of human experts to generate time constraints. Specifically, PaTeCon dynamically attaches class restriction to candidate constraints according to their measuring scores.We evaluate PaTeCon on two large-scale datasets based on Wikidata and Freebase respectively. The experimental results show that pattern-based automatic constraint mining is powerful in generating valuable temporal constraints., Comment: Accepted by AAAI23

For two decades, two-dimensional carbon species, including graphene, have been the core of research in pursuing next-generation logic applications beyond the silicon technology. Yet the opening of a gap in a controllable range of doping, whilst keeping high conductance outside of this gapped state, has remained a grand challenge in them thus far. Here we show that, by bringing Bernal-stacked bilayer graphene in contact with an anti-ferromagnetic insulator CrOCl, a strong insulating behavior is observed in a wide range of positive total electron doping $n_\mathrm{tot}$ and effective displacement field $D_\mathrm{eff}$ at low temperatures. Transport measurements further prove that such an insulating phase can be well described by the picture of an inter-layer excitonic state in bilayer graphene owing to electron-hole interactions. The consequential over 1 $\mathrm{G\Omega}$ excitonic insulator can be readily killed by tuning $D_\mathrm{eff}$ and/or $n_\mathrm{tot}$, and the system recovers to a high mobility graphene with a sheet resistance of less than 100 $\mathrm{\Omega}$. It thus yields transistors with "ON-OFF" ratios reaching 10$^{7}$, and a CMOS-like graphene logic inverter is demonstrated. Our findings of the robust insulating phase in bilayer graphene may be a leap forward to fertilize the future carbon computing., Comment: 10 pages, 4 figures

The understanding of time expressions includes two sub-tasks: recognition and normalization. In recent years, significant progress has been made in the recognition of time expressions while research on normalization has lagged behind. Existing SOTA normalization methods highly rely on rules or grammars designed by experts, which limits their performance on emerging corpora, such as social media texts. In this paper, we model time expression normalization as a sequence of operations to construct the normalized temporal value, and we present a novel method called ARTime, which can automatically generate normalization rules from training data without expert interventions. Specifically, ARTime automatically captures possible operation sequences from annotated data and generates normalization rules on time expressions with common surface forms. The experimental results show that ARTime can significantly surpass SOTA methods on the Tweets benchmark, and achieves competitive results with existing expert-engineered rule methods on the TempEval-3 benchmark., Comment: Accepted to Findings of EMNLP 2021

In crystals, the duplication of atoms often follows different periodicity along different directions. It thus gives rise to the so called anisotropy, which is usually even more pronounced in two dimensional (2D) materials due to the absence of $\textbf{z}$ dimension. Indeed, in the emerging 2D materials, electrical anisotropy has been one of the focuses in recent experimental efforts. However, key understandings of the in-plane anisotropic resistance in low-symmetry 2D materials, as well as demonstrations of model devices taking advantage of it, have proven difficult. Here, we show that, in few-layered semiconducting GaTe, electrical conductivity along $\textbf{x}$ and $\textbf{y}$ directions of the 2D crystal can be gate tuned from a ratio of less than one order to as large as 10$^{3}$. This effect is further demonstrated to yield an anisotropic memory resistor behaviour in ultra-thin GaTe, when equipped with an architecture of van der Waals floating gate. Our findings of gate tunable giant anisotropic resistance (GAR) effect pave the way for potential applications in nano-electronics such as multifunctional directional memories in the 2D limit., Comment: 9 pages, 4 figures

Atomically-thin 2D semiconducting materials integrated into van der Waals heterostructures have enabled architectures that hold great promise for next generation nanoelectronics. However, challenges still remain to enable their full acceptance as compliant materials for integration in logic devices. Two key-components to master are the barriers at metal/semiconductor interfaces and the mobility of the semiconducting channel, which endow the building-blocks of ${pn}$ diode and field effect transistor. Here, we have devised a reverted stacking technique to intercalate a wrinkle-free h-BN tunnel layer between MoS$_{2}$ channel and contacting electrodes. Vertical tunnelling of electrons therefore makes it possible to suppress the Schottky barriers and Fermi level pinning, leading to homogeneous gate-control of the channel chemical potential across the bandgap edges. The observed unprecedented features of ambipolar ${pn}$ to ${np}$ diode, which can be reversibly gate tuned, paves the way for future logic applications and high performance switches based on atomically thin semiconducting channel., Comment: 23 pages, 5 main figures + 9 SI figures