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This work demonstrates the valence band-edge effective work function (φm,eff) of a titanium nitride (TiN) gate with a hafnium oxide (HfO2) dielectric using a cost-effective, low-complexity gate-first integration scheme. Aluminum (Al) ion implantation following TiN gate stack formation yielded a φm,eff of 5.0 eV without an equivalent oxide thickness penalty. Additionally, the incorporation of fluorine (F) into the HfO2 dielectric by the channel implantation approach further improved φm,eff to 5.1 eV. This technique for modulating φm,eff has potential for threshold-voltage tuning without any process complexity in high-k/metal gate low-power applications.

The effects of post-NH3 plasma nitridation on device's hot-carrier instability and low-frequency noise in the Hf-based high-κ/metal-gate n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) with gadolinium (Gd) cap layers are investigated. With postnitridation, the direct-current and 1/f noise characteristics can be improved apparently. Moreover, a hot-carrier stressing-induced threshold voltage shift can be also suppressed despite of a similar transconductance degradation when comparing with that in the device without nitridation. With the charge-pumping and low-frequency noise measurements, we find that the bulk- and interfacial-trap densities can be reduced with nitrogen incorporation. The reduction of bulk and interfacial traps can be contributed to the suppression of Gd diffusion into a high-κ layer. In this paper, appropriate post-NH3 plasma nitridation can improve the device performance and reliability and low-frequency noise for a gate-first high-κ/metal-gate nMOSFET with a Gd cap layer.

The interactions of shallow trench isolation (STI) stress and various mobility enhancement approaches in silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) have been systematically studied. Strong interactions between STI stress and contact etch stop layer (CESL) stress on channel mobility were observed which was attributed to the amplification of CESL channel tensile stress with length of diffusion (LOD) reduction. In this work, an almost completely reversed P-channel metal oxide semiconductor field-effect transistor (PMOSFET) mobility-LOD trend in both /(100) and /(100) oriented SOI wafers was found, which is caused by the reversed polarity of piezoresistance coefficients. On the other hand, charge pumping leakage was enhanced by the post-gate oxide stress (CESL stress) only, and was not affected by any stress applied prior to the gate oxidation step (STI stress).

In this letter, the effect of adding ZrO2 to different positions in an HfO2-based high-k (HK) gate-stack is investigated by a low-frequency (1/ f ) noise measurement. The tested nMOSFETs are fabricated using 28-nm gate-last HK/metal-gate technology with a ~ 1-nm SiO2 interfacial layer. The 1/f noise mechanism of these devices is described by the carrier number fluctuation, and the extracted trap densities (Nt)are 8.9 × 1018-5.1 × 1019 eV-1 cm-3. However, reference devices with a pure ZrO2 gate dielectric exhibit 1/f noise characteristics that are consistent with the unified model, which incorporates both the carrier number and the correlated mobility fluctuations. The reference devices are with lower Nt values in the range of 5.8 × 1017-2.4 × 1018 eV-1 cm-3. In addition, there is an increase in Nt as the initial HfO2 layer becomes thicker.These results show that the trapping behavior is mainly dominated by the HfO2 film and is dependent on the thickness of the initial HfO2 layer in the ZrO2/HfO2/SiO2gate-stack.

Low-frequency (1/f) noise characteristics of 28-nm nMOSFETs with ZrO2/SiO2 and HfO2/SiO2 dielectric gate stacks have been investigated. The observed lower 1/f noise level in ZrO2 devices, as compared with that in HfO2 devices, is attributed to the reduction in tunneling attenuation length and in trap density simultaneously. Experimental results showed that the trap behavior of ZrO2/SiO2 dielectric gate stack changes not only the trap location from a high-k layer to a SiO2 interfacial layer but also the noise-dominated mechanism from carrier number fluctuation to the unified fluctuation model, which includes number fluctuation and correlated mobility fluctuation.

In this letter, performance and reliability of high-k/metal gate MOSFETs can be effectively improved using post metallization annealing. Both oxygen and nitrogen were shown to diffuse into a high-k/SiO2 interfacial layer to suppress the formation of oxygen vacancy, thus reducing the gate leakage current without increasing effective oxide thickness. In particular, with appropriate oxygen annealing, gate-induced drain leakage, drain-current degradation, and gate leakage current variation of high- k/metal gate-last MOSFETs can be efficiently suppressed.

In this letter, the effect of nitrogen incorporation in a Gd cap layer on the reliability of Hf-based high- k/metal-gate nMOSFETs is investigated in detail. NH3 post plasma treatment was implemented after deposition of the Hf-silicate (HfO2 or HfSiOx) to improve the channel interface state. The Gd cap layer was added on the top of the Hf-based high-k/metal gate for reducing the threshold voltage. However, the nitrogen atoms incorporated in the gate stack via the NH3 plasma treatment could also diffuse into the Gd cap layer, thus blocking the Gd ions at the top of the Hf-based high-k /metal gate, which then generate bulk charges to degrade the device's positive bias instability significantly. We identify the diffusion of nitrogen in the Gd cap layer as well as the location of trap defects in the Hf-based high-k/metal gate with secondary ion mass spectrometry, flicker-noise, and charge-pumping measurements.

A fully silicided (FUSI) metal gate process is merged with ultimate spacer process (USP) strain engineering to effectively enhance the performances of deep nano complementary metal oxide semiconductor field effect transistor (CMOSFET). Using the merged FUSI–USP process, the FUSI gate can be processed with the source/drain region silicide in one step, and the poly gate can be thinned to less than 300 A, thus shortening the distance between the strain contact etch stop layer and the channel to generate higher stress. Therefore, Ion gain up to 28% can be achieved in an n type MOSFET with tensile-stress, and 40% in a p type MOSFET with compressive-stress.

The use of hybrid orientation technology with direct silicon bond wafers consisting of a (110) crystal orientation layer bonded to a bulk (100) handle wafer provides exciting opportunities for easier migration of bulk CMOS designs to higher performance materials, particularly (110) Si for PMOSFETs for higher hole mobility. In this letter, a 3times mobility improvement and 36% drive current gain were achieved for PMOSFETs on (110) substrates. A systematic investigation of PMOSFET reliability was conducted, and significant degradation of negative bias temperature instability lifetime on (110) orientation was observed due to higher density of dangling bonds. We also report the crystal orientation dependence on ultrathin nitrided gate oxide time-dependent dielectric breakdown.

For the first time, a simple CMOS fully silicided (FUSI) process achieving n/pMOS band-edge work function was demonstrated, which is fully compatible with conventional CMOS process. Dual-work-function CMOS FUSI, with a wide range of 800 mV, was achieved by implantation of Yb into the poly of the nMOS gate (4.1-eV work function) and Ga into the poly of the pMOS gate (4.9-eV work function), respectively. The placement of the tuning elements at the metal/dielectric interface was engineered with the thermal budget, as well as the implant dose and species.

In this letter, mobility improvements by stress contact etch stop layer (CESL) in a strained 90-nm nMOSFET, with and without notched-gate structure, were studied in detail. Compared to the conventional vertical gate, a device with notched gate shows an extra 7% NMOS ION enhancement for the increased stress in the channel region and the less effect of the halo-implanted impurity on channel. Both simulations with TCAD software and measurements confirm that the notched-gate structure efficiently enhances the generation of high tensile stress on the channel region from the CESL and more localized pocket implant

A novel strain engineering technique for a fully silicided (FUSI) metal gate called contact etch stop layer (CESL)-enveloped FUSI was developed for the first time. A CESL was deposited prior to the FUSI RTP2 (the second rapid thermal process of FUSI gate formation) to confine the NixSi FUSI. Then, the phase transfer and volume change of the enveloped FUSI after RTP2 induced a tensile stress to enhance ION. For example, 500 degC RTP2 induced 1-GPa tensile stress on a blanket wafer test and gained 10% improvement in the ION of the n-channel metal-oxide-semiconductor. The mechanisms of the improvement were also nicely supported by transmission-electron-microscope cross-section analysis, X-ray-diffraction spectrum, and simulation confirmation data

In this letter, based on both experimental investigations and simulation confirmation, it was found that a strained contact etch stop layer over the thin silicon layer of a partially depleted silicon-on-insulator (PD-SOI) will induce high stress on the buried-oxide/silicon interface. Additionally, the interface stress increases with decrease of silicon thickness TSI, thus enhancing the current of the MOSFET, e.g., as TSI shrinks from 90 to 50 nm, current enhancement for PD-SOI n-channel MOS increased from 7% to 12% due to the increase of interface stress. The results are expected to be more significant for devices with thinner TSI such as fully depleted silicon-on-insulator and multigate devices

EOT scale down is a critical issue in LaO/AlO capped Hf-based devices, because it will result in serious V FB roll-off. The incorporation of capping layer induces more traps in the gate stack. These traps are oxygen vacancy related defects and are sensitive to reliability stress. By using the oxygen vacancies detection method, we demonstrate that these oxygen vacancy defects are near to IL (SiO 2 ). In addition, the interface states are found strongly dependent on the V FB roll-off, especially for IL scaled device.

The impact of aluminum (Al) implantation into TiN/HfO2/ SiO2 on the effective work function is investigated. Al implanted through poly-Si cannot attain sufficient flatband voltage (VFB) shift unless at higher implantation energy. Al implanted through TiN at 1.2 keV with a dose of 5 × 1015 cm-2 raised the VFB to about 250 mV compared with a nonimplanted gate stack. Moreover, the VFB shift can be up to about 800 mV at 2 keV with the same dose level accompanied with slightly equivalent oxide thickness penalty and gate leakage current degradation. Optimized process window to control Al diffusion depth was essential to minimize these impacts.

The use of hybrid orientation technology (HOT) with direct silicon bond (DSB) wafers consisting of a (110) crystal orientation layer bonded to a bulk (100) handle wafer provides promising opportunities for easier migration of bulk CMOS designs to higher performance materials. In this work, the integration of shallow-trench-isolation (STI) after amorphization and templated recrystallization (ATR) scheme for converting surface orientation from (110) to (100) was investigated. By optimizing the trade-off between ATR-induced triangular morphology and DSB layer thickness, a 3X holes mobility improvement and 36% drive current gain were achieved for PMOSFETs fabricated on (110) plane using DSB-HOT. In addition, un-loaded ring oscillators fabricated using DSB substrates show a 38% improvement compared with control CMOS on (100) wafers.

This paper describes a comprehensive study of the impact of tCESL (tensile Contact Etch Stop Liner) and cCESL (compressive Contact Etch Stop Liner) on tensile metal gate MuGFET with SOI and globally strained SOI (sSOI) substrates. We have demonstrated that tCESL and cCESL can be effectively used on MuGFETs to provide performance gain. Since tCESL and cCESL affect NMOS and PMOS mobilities in the opposite directions, dual stress liner technology with high-stress cCESL is needed for optimal CMOS MuGFET performance.

The impact of post metal-deposition annealing (PMA) on the trap behavior of high-k/metal-gate metal-oxide-semiconductor field-effect transistors has been studied using drain current random telegraph noise (RTN). The RTN phenomenon is influenced by both trap positions and trap energy, thus corresponding with the PMA passivation mechanism. We found that trap positions in mono-metal-layer annealed (TiN annealed) devices are closer to the TiN/HfO2 interface due to the substitution of nitrogen atoms by oxygen atoms inside the TiN layer. However, replaced nitrogen atoms from TaN can passivate nitrogen defects in TiN that improves device characteristics in dual-metal-layer annealed (TiN/TaN annealed) devices.

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