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BACKGROUND:Intra-body communication is a new wireless scheme for transmitting signals through the human body. Understanding the transmission characteristics of the human body is therefore becoming increasingly important. Electrostatic-coupling intra-body communication system in a ground-free situation that integrate electronic products that are discretely located on individuals, such as mobile phones, PDAs, wearable computers, and biomedical sensors, are of particular interest. MATERIALS AND METHODS:The human body is modeled as a simplified Resistor-Capacitor network. A virtual ground between the transmitter and receiver in the system is represented by a resister-capacitor network. Value of its resistance and capacitance are determined from a system perspective. The system is characterized by using a mathematical unit step function in digital baseband transmission scheme with and without Manchester code. As a result, the signal-to-noise and to-intersymbol-interference ratios are improved by manipulating the load resistor. The data transmission rate of the system is optimized. A battery-powered transmitter and receiver are developed to validate the proposal. RESULTS:A ground-free system fade signal energy especially for a low-frequency signal limited system transmission rate. The system transmission rate is maximized by simply manipulating the load resistor. Experimental results demonstrate that for a load resistance of 10k-50k Ω, the high-pass 3 dB frequency of the band-pass channel is 400kHz-2MHz in the worst-case scenario. The system allows a Manchester-coded baseband signal to be transmitted at speeds of up to 20M bit per second with signal-to-noise and signal-to-intersymbol-interference ratio of more than 10 dB. CONCLUSION:The human body can function as a high speed transmission medium with a data transmission rate of 20Mbps in an electrostatic-coupling intra-body communication system. Therefore, a wideband signal can be transmitted directly through the human body with a good signal-to-noise quality of 10 dB if the high-pass 3 dB frequency is suitably selected.

This paper presents a method of thermal balancing for monolithic power integrated circuits (ICs). An on-chip temperature monitoring sensor that consists of a poly resistor strip in each of multiple parallel MOSFET banks is developed. A temperature-to-frequency converter (TFC) is proposed to quantize on-chip temperature. A pulse-width-modulation (PWM) methodology is developed to balance the channel temperature based on the quantization. The modulated PWM pulses control the hottest of metal-oxide-semiconductor field-effect transistor (MOSFET) bank to reduce its power dissipation and heat generation. A test chip with eight parallel MOSFET banks is fabricated in TSMC 0.25 μm HV BCD processes, and total area is 900 × 914 μm2. The maximal temperature variation among the eight banks can reduce to 2.8 °C by the proposed thermal balancing system from 9.5 °C with 1.5 W dissipation. As a result, our proposed system improves the lifetime of a power MOSFET by 20%.