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Grayscale mask creation has for the most part been restricted to over-simplified optical and resist models usually based on a contrast curve approach. While this technique has proven to work for microstructures of large dimensions (ten to hundreds of micrometers), its capability has not been assessed for microstructures with smaller dimensions. In this paper, a rigorous lithographic model has been developed in Python to simulate the process of imaging, exposure and development of an i-line photoresist. Using this model, a mask data preparation algorithm capable of optimizing simultaneously both the size and position of the dots on a grayscale mask has been implemented. Experimental results after development of the photoresist confirm the capability of our mask data preparation algorithm to achieve microstructures with dimensions ranging between 1 to $3~\mu \text{m}$ . [2021-0018]

Galileo Galilei once quoted: “Measure what is measurable, and make measurable what is not so”. In silicon manufacturing R&D phase, it often happens that engineers would like to access some parameter values that are not easy, even impossible to measure. When looking at a CDSEM image, the parameters of interest seem easy to extract but in practice getting access to them in a robust and reliable way is not always simple. Developing a contour-based metrology tool coupling robust contour extraction with a comprehensive contour metrology environment could help to bridge this gap. In previous works, it has been shown that SEM images contain significant amounts of information that can be extracted and analyzed using efficient contour extraction and analysis toolboxes [1, 2]. Also, the concept of implementing remote contour-based metrology has been introduced. The present work continues to unveil what can be achieved with such solutions. For that, the example of implant layers’ process assumption will be explored. During this process step, counter doping problems can occur for example when the distance between layers deviates from nominal. Therefore, it is crucial for design rule control to measure some critical dimensions such as minimum distance between layers, corner rounding, slope, etc. However, given the characteristics of the different structures in the images, which may come from different layers and/or processes steps, the measurements are not straightforward to extract with standard CDSEM metrology algorithms. Moreover, recipes are complex to setup, measurements by themselves are not very stable, and usually an indirect determination of the key figure is performed. In this paper, we will show that multilayer contour-based metrology, mixing image contour and GDS layout, allows to overcome the previously mentioned difficulties, as well as to generate measurements that are not possible to be performed by using standard algorithms.

CMOS imaging has experienced significant developement in the last decades. At the center of this progress lies the pixel, composed of a light sensitive area (photodiode) coupled to a network of transistors. As the pixels sizes shrink, the light sensitive area gets smaller and requires light focusing assistance. To address this issue, microlenses are added to the top of the pixels stack. The microlenses are made of polymer resist transparent to the wavelength of interest. Creating such structures is not straightforward and requires complex process steps, especially when arrays of multiple shapes and sizes are needed. The grayscale approach appears as a promising alternative since this unconventional lithography method can produce variable shapes and sizes in a single lithography step. Mask data preparation is the most critical step for grayscale lithography. A widespread strategy is to experimentally establish the relationship between a given dose (corresponding to a specific chromium density on the mask) and the remaining resist thickness after development. The relationship, also known as contrast curve, is used as a transfer function to compute a suitable mask for the given resist. Our approach is to create a simplified grayscale model able to predict the resist response under any given mask and illumination condition. Using the classic contrast curve approach we have designed a mask composed of sub 5μm patterns and evaluated the resist profile prediction of the contrast curve approach compared to our grayscale model on various patterns including microlenses, pyramids and bowl shapes. Reults show that the contrast curve approach is no longer appropriate when the dimensions reduce below 5μm.

There has been a significant increase of optical applications in the last decade, either embedded into complex multifunction devices such as smartphones, or for imaging purpose as cameras. Core of such optical systems are microlens arrays, used for light gathering or light emitting. The most commonly used manufacturing method by the industry is the thermal reflow of photoresist polymer. The method consists in melting previously patterned photoresist dots in order to form the lenses. But the resist shaping into a microlens is not as straight forward, since the final microlens needs to match shaping criteria to maximize the device optical efficiency. The optimization of the microlens 3D shape is thus an empiric and iterative work, where several lithography and reflow process variations are explored. Photomask reorder might also be needed in order to finally reach the final targeted microlens. All of this results in a costly and time consuming process tuning work. A low cost alternative option to overcome this practical issue and make the overall microlens optimization process easier would be to have at disposal a resist reflow simulation tool, which could predict the photoresist shaping evolution through melt and cure steps. This would help designers and lithographer to evaluate beforehand the final shape of a certain design at the end of the process flow. It would then offer the possibility to identify from the start the correct design to embed onto the photomask guaranteeing the fabrication of the desired microlens. A 3D compatible and computation efficient reflow simulation software is proposed in this paper, in line with a Design Process Technology Co-optimization (DTCO) approach. It allows the fast 3D reflow simulations of hundreds of different resist patterns, taking as input a CAD design and returning the corresponding 3D microlens that will be formed. The purpose of this paper is to present the developed reflow modeling software solution and its calibration methodology. The use of the proposed alternative simulation flow for microlens optimization in a Resolution Enhancement Technics (RET) environment will also be described.

In semiconductor fabs, electron microscopes are key equipment for metrology, failure analysis, physical characterization and defect review classification. In a wafer fab like ST Crolles 300mm, CDSEMs are generating more than 20 Million of images per year. The image is by itself a raw material on which the metrology is performed. It is needed to get access to CD which is very often a single value extracted. If the CD is in specification, it is very unlikely that someone will look at the picture. If someone would do so in a systematic way, it would see that there is much more information available in the image than a single CD value. Unfortunately, most of this information passes under the radar of SPC charts and is somehow wasted. This paper presents results obtained by CDSEM image contour analysis from various kind of technologies and applications in manufacturing in our fab. These results show that images contain significant amounts of information that can be extracted and analyzed using an efficient contour extraction and analysis toolbox. Process variability of complex shapes can be shown, robust layer to layer metrics can be computed, pattern shifting, shape changes, image quality and many others too. This opens new possibilities for process control and process variability monitoring and mitigation.

In this work, we evaluate through rigorous coupled-wave analysis simulations the effect of various process-related inaccuracies on plasmonic filters performance, especially regarding cross-shaped-hole arrays. Focusing exclusively on CMOS-compatible materials, we demonstrate the potential of these structures for reliable integration and fabrication at wafer level. A high monitoring of the deposition parameters is required to control the transmission level and the resonant wavelength of the filters. Optical proximity calculations show that double patterning is a way to limit corner rounding and to avoid losing the resonant mode of the crosses. The impacts on plasmon resonances of the metal oxidation, or a sloped profile after metal etching, are evaluated. These results allow for a good anticipation regarding process issues to realize efficient plasmonic filters.

Design For Manufacturing (DFM) is becoming essential to ensure good yield for deep sub micron technologies. As design rules cannot anticipate all manufacturing marginalities resulting from problematic 2D patterns, the latter has to be addressed at design level through DFM tools. To deploy DFM strategy on back end levels, STMicroelectronics has implemented a CAD solution for lithographic hotspots search and repair. This allows the detection and the correction, at the routing step, of hotspots derived from lithographic simulation after OPC treatment. The detection of hotspots is based on pattern matching and the repair uses local reroute ability already implemented in Place and Route (PnR) tools. This solution is packaged in a Fast LFD Kit for 28 nm technology and fully integrated in PnR platforms. It offers a solution for multi suppliers CAD vendors routed designs. To ensure a litho friendly repair, the flow integrates a step of local simulation of the rerouted zones. This paper explains the hotspots identification, their detection through pattern matching and repair in the PnR platform. Run time, efficiency rate, timing and RC parasitic impacts are also analyzed.

The 2x nm generation of advanced designs presents a major lithography challenge to achieve adequate correction due to the very low k1 values. The burden thus falls on resolution enhancement techniques (RET) in order to be able to achieve enough image contrast, with much of this falling to computational lithography. Advanced mask correction techniques can be computationally expensive. This paper presents a methodology that enables advanced mask quality with the cost of much simpler methods. Brion Technologies has developed a product called Flexible Mask Optimization (FMO) which identifies hotspots, applies an advanced technique to improve them, performs model based boundary healing to reinsert the repaired hotspot cleanly (without introducing new hotspots), and then performs a final verification. STMicroelectronics has partnered with Brion to evaluate and prove out the capability and performance of this approach. The results shown demonstrate improved performance on 2x nm node complex 2D hole layers using a hybrid approach of rule based sub resolution assist features (RB-SRAF) and model based SRAF (MB-SRAF). The effective outcome is to achieve MB-SRAF levels of quality but at only a slightly higher computational cost than a quick, cheap rule based approach.

The resolution enhancement through lithography hardware (wavelength and Numerical Aperture) has come to a stop putting the burden on computational lithography to fill in the resulting gap between design and process until the arrival of EUV tools. New Computational Lithography techniques such as Optical Proximity Correction (OPC), Sub Resolution Assist Feature (SRAF), and Lithography Friendly Design (LFD) constitute a significant transformation of the design. These new Computational Lithography applications have become one of the most computationally demanding steps in the design process. Computing farms of hundreds and even thousands of CPUs are now routinely used to run these applications. The 28nm node presents many difficulties due to low k1 lithography whereas the 20nm requires double patterning solutions. In this paper we present a global view of enhanced RET and DFM techniques deployed to provide a robust 28nm node and prepare for 20nm. These techniques include advanced OPC manipulation through end user IP insertion into EDA software, optimized sub resolution assist features (SRAF) placement and pixilated OPC. These techniques are coupled with a fast litho print check, aka LFD, for 28nm P&R.

Image sensors are now part of our daily life through smartphones and other mobile devices. The increasing quality of images is linked to the important progress of technologies. Imaging technologies allow the association of imaging capture modules and integrated circuits. Those modules are built with photosensibles matrix that react to specific wavelength according to the application. The matrix need the fabrication of microlenses that make possible the capture and focalisation of light toward each pixel. Firstly, the student will characterise the resin used in microlenses fabrication in order to create a model that can simulate the resin's response. A methodology of design and preparation specific to grayscale masks also need to be established. In order to do that, several iterations of mask fabrication alongside 3D caracterisations will be needed. Their purpose is to check the performance and precision of modelling tools composing this fabrication process. Once the methodoly established, it will be used to propose 3D shapes of effective and innovating microlenses while investigating the key parameters such as shape, mask type, the fine optimization of lithography process, optimisation of materials (reflectivity, piling, films thickness...). In a long term vision, this project will be used to create a comparison of microlenses prformances during the thesis with the industrial reference process to show the benefit of such model., Les capteurs d'images font désormais partie de notre quotidien à travers les smartphones et autres appareils mobiles. La qualité croissante des images délivrées est liée au progrès importants des technologies mises en oeuvre. Les technologies Imageur permettent d'associer des modules de capture d'image avec des circuits intégrés. Ces modules sont construits avec des matrices de pixels photosensibles qui réagissent à certaines longueurs d'onde en fonction du type d'application visé. Ces matrices nécessitent la fabrication de microlentilles qui permettent de capturer et de focaliser les rayons lumineux vers chaque pixel. Dans un premier temps l'étudiant(e) aura comme but de caractériser les résines propres à la fabrication des microlentilles et de créer un modèle pour simuler la réponse de la résine. Une méthodologie de design et de préparation de données spécifique aux masques de type Grayscale devra également être établie. Pour ce faire, plusieurs itérations de fabrication de masque couplées à des caractérisations 3D seront nécessaires pour vérifier la performance et la précision des outils de modélisation composant ce processus de fabrication. Une fois cette méthodologie établie, elle sera utilisée afin de proposer des formes 3D de microlentilles performantes et innovantes, en investiguant tous les paramètres clefs tels que la forme et le type de masque, une optimisation fine du ou des procédé(s) de lithographie, l'optimisation des matériaux utilisés (réflectivité, empilement, épaisseurs des couches...). Dans une vision à plus long terme, ce projet permettra de faire un comparatif de performance des microlentilles réalisées durant la thèse avec le procédé de référence industriel pour démontrer le gain d'une telle méthodologie.