261 results on '"Charles J. Alpert"'
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2. MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes.
3. Stitch aware detailed placement for multiple e-beam lithography.
4. Stitch aware detailed placement for multiple E-beam lithography.
5. Pacman: driving nonuniform clock grid loads for low-skew robust clock network.
6. Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography.
7. Clock power minimization using structured latch templates and decision tree induction.
8. Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths.
9. CATALYST: planning layer directives for effective design closure.
10. Routing congestion estimation with real design constraints.
11. MAPLE: multilevel adaptive placement for mixed-size designs.
12. Keep it straight: teaching placement how to better handle designs with datapaths.
13. Placement: Hot or Not?
14. ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite.
15. WRIP: logic restructuring techniques for wirelength-driven incremental placement.
16. The DAC 2012 routability-driven placement contest and benchmark suite.
17. Guiding a physical design closure system to produce easier-to-route designs with more predictable timing.
18. GLARE: global and local wiring aware routability evaluation.
19. The ISPD-2011 routability-driven placement contest and benchmark suite.
20. Quantifying academic placer performance on custom designs.
21. Ultra-fast interconnect driven cell cloning for minimizing critical path delay.
22. ITOP: integrating timing optimization within placement.
23. What makes a design difficult to route.
24. Design-hierarchy aware mixed-size placement for routability optimization.
25. New placement prediction and mitigation techniques for local routing congestion.
26. Detecting tangled logic structures in VLSI netlists.
27. A faster approximation scheme for timing driven minimum cost layer assignment.
28. CRISP: Congestion reduction by iterated spreading during placement.
29. A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion.
30. Techniques for scalable and effective routability evaluation.
31. Fast interconnect synthesis with layer assignment.
32. RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm.
33. A polynomial time approximation scheme for timing constrained minimum cost layer assignment.
34. Pyramids: an efficient computational geometry-based approach for timing-driven placement.
35. Path smoothing via discrete optimization.
36. The coming of age of physical synthesis.
37. Hippocrates: First-Do-No-Harm Detailed Placement.
38. Fast Electrical Correction Using Resizing and Buffering.
39. Probabilistic Congestion Prediction with Partial Blockages.
40. The nuts and bolts of physical synthesis.
41. RQL: Global Placement via Relaxed Quadratic Spreading and Linearization.
42. Fast algorithms for slew constrained minimum cost buffering.
43. Timing-driven Steiner trees are (practically) free.
44. A semi-persistent clustering technique for VLSI circuit placement.
45. The ISPD2005 placement contest and benchmark suite.
46. An efficient surface-based low-power buffer insertion algorithm.
47. Practical techniques to reduce skew and its variations in buffered clock networks.
48. Computational geometry based placement migration.
49. Making fast buffer insertion even faster via approximation techniques.
50. Placement stability metrics.
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