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As there are more things connected, more attacks through the internet occur. To protect the connected devices from being hacked, the security of each device becomes very important. The root of trust, which provides the secure storage of the secret key and the operation of security services, such as confidentiality, integrity, and authenticity, is the most important element in the chip to safeguard the chip and the operation of the system. A quantum tunneling PUF (Physically Unclonable Functions) can be formed by using the oxide variations during manufacturer processes. The quantum tunneling PUF stores the quantum signature inside the ultra-thin oxide, which is random, unique, stable, reliable, radiation-hardened, and non-traceable, such that it can play the role of fingerprint of the chip. The PUF-based hardware Root of Trust provides high security with high reliability whilst retaining a low cost for the applications in IoT, AI, autonomous driving, block-chains and 5G.

Many high voltage complementary metal–oxide–semiconductor (HV-CMOS) processes are modified from a standard 5 V CMOS process by adding an N-type heavily doped layer under the P-well of a HV-PMOS drain terminal to isolate a high voltage P-well from a grounded P-substrate. The limitation of breakdown voltage is dominated by P-well concentration and junction depth. For designing a certain breakdown voltage (BVdss) for a HV-PMOS, the original 5 V CMOS P-well concentration should be decreased, which could degrade 5 V CMOS characteristics, such as NMOS punch through and latch-up immunity. In this study, we demonstrate a novel HV-PMOS based on a split N-type buried layer (NBL), which provides a high BVdss in a HV-CMOS process. The newly proposed device with NBL split under the P-well of a drain electrode increases BVdss without degrading specific on-resistance (Ron,sp) and any added process complexity. From this result, P-well concentration could be increased to improve both 5 V NMOS characteristics and HV-PMOS Ron,sp.

In this paper, a novel ballistic-injection AND-type (BiAND) split gate flash memory, with a trench select gate and buried n+ source is proposed. The ballistic source side injection (BSSI) programming mechanism is performed and realized in a contactless AND array, which features high programming efficiency, 10-3–10-4 and small cell size of 5 F2. In addition, both the programming speed and read current is enhanced by the shared select gate structure. The BiAND flash memory is thus promising for low-voltage, high efficient, fast speed, scalable and high reliability non-volatile memory applications.

In this work a new multilevel programming approach employing the new self-adjusted dynamic source (SADS) structure for p-channel flash memory is studied. The memory unit is composed of a current source and a p-channel stacked-gate transistor. Using SADS structure, the final source voltage, which is not grounded, is found to be dependent on the applied drain voltage. Programmed threshold voltage is observed to be proportional to the final source voltage. Adjusting drain voltages during programming results in the predictable multilevel threshold voltages due to the self-adjusted dynamic source mechanism. The programming drain current in p-channel flash memory can be limited to a low level to achieve low power programming by adjusting the conducting current of the current source. Furthermore, the drain disturbance, which alters the stored charge of other memory cells, can be suppressed in the SADS structure by shutting off the current source and employing negative word line voltages on the unselected cells.

A novel process which uses N/sub 2//sup +/ implantation into polysilicon gates to suppress the agglomeration of CoSi/sub 2/ in polycide gated MOS devices is presented. The thermal stability of CoSi/sub 2//polysilicon stacked layers can be dramatically improved by using N/sub 2//sup +/ implantation into polysilicon. The sheet resistance of the samples without N/sub 2//sup +/ implantation starts to increase after 875/spl deg/C RTA for 30 s, while the sheet resistance of CoSi/sub 2/ film is not increased at all after 950 and 1000/spl deg/C RTA for 30 s if the dose of nitrogen is increased up to 2/spl times/10/sup 15/ cm/sup -2/ and 6/spl times/10/sup 15/ cm/sup 2/, respectively, and TEM photographs show that the agglomeration of CoSi/sub 2/ film is completely suppressed. It is found that the transformation to CoSi/sub 2/ from CoSi is impeded by N/sub 2//sup +/ implantation such that the grain size of CoSi/sub 2/ with N/sub 2//sup +/ implantation is much smaller than that without N/sub 2//sup +/ implantation. As a result, the thermal stability of CoSi/sub 2/ is significantly improved by N/sub 2//sup +/ implantation into polysilicon.

An AND-type split-gate Flash memory cell with a trench select gate and a buried n/sup +/ source is proposed. This cell, programmed by ballistic source side injection (BSSI), can provide high programming efficiency with a cell size of 5F/sup 2/. Furthermore, both the programming speed and the read current are enhanced by the shared select gate configuration.

Red-shift of photoluminescence (PL) spectra and increasing intensity after subsequent annealing have been observed in plasma-enhanced chemical-vapor-deposition (PECVD) silicon-rich-oxide (SRO). Based on FTIR results, however, PECVD SRO does experience chemical and structural changes during post-deposition annealing and becomes denser. Besides, the enhanced tunneling characteristics of MOS capacitor using SRO thin film as injector due to nanocrystalline silicon (nc-Si) in SRO thin film is also observed. These results strongly suggest the luminescence and the enhanced tunneling characteristics originate from the quantum size effect of nc-Si. In this paper, a Si-island model is proposed to delineate the gradual red-shift phenomenon of PL spectra.

This paper presents the embedded OTP fuse in standard CMOS logic compatible process without additional mask. The embedded OTP fuse can be programmed in 100/spl mu/s per byte and be accessed in 6ns for 32 bits at once. The 32-bit OTP fuse takes less than 0.0085mm/sup 2/ in 0.25/spl mu/m CMOS process and has 10-year data retention at 85/spl deg/C.

In this paper, data retention for various top and bottom oxide (tunnel oxide) SONOS cells has been extensively investigated. For the first time, a leakage current separation technique has been developed to distinguish the two leakage current components via thermionic and direct tunneling (DT) in the ONO layer. Results show that the short-term leakage is dominated by the direct tunneling, while the long-term leakage is dominated by the thermionic emission. The direct tunneling through either tunnel or blocking oxide can also be identified experimentally. These results are useful toward an understanding of the scaling of the SONOS cell with focus on its reliabilities.

Buried bit-line NAND (BiNAND) Flash is newly proposed to achieve low voltage programming/erase and facilitate multi-level storage. Due to the buried bit-line, the required high program/erase voltage for FN tunneling can be divided between word-line and bit-line and therefore minimizes the disturbance. The negative programmed threshold voltage also facilitates the operation of multi-level storage due to high array conductivity.

A novel hot carrier mechanism "band-to-band tunneling hole induced bipolar hot electron (BBHBHE)" is, for the first time, observed in the new P-channel MOSFET with an embedded NPN bipolar transistor at the source side. Operating in the band-to-band tunneling region (i.e. positive gate voltage), the new P-cell generates 100/spl times/ gate current larger than conventional PMOS, while, in normal conduction condition (i.e. negative gate voltage), the cell features 5/spl times//spl sim/16/spl times/ drain current amplification compared to conventional devices. This work discusses the optimization of the new cell and design guideline to improve cell characteristics. By using the BBHBHE mechanism, the superior gate current is a very promising feature for future flash memory requiring programming-speed of tens of nanoseconds.

A novel 'decoupled C-V' technique is proposed to characterize the channel and overlap capacitances of miniaturized MOSFET's. This method successfully decouples channel capacitance from overlap capacitance in submicron CMOS devices. The intrinsic channel capacitance can be well modeled by the quasi-static C-V theory. It allows the accurate determination of the effective channel length and effective channel doping concentration in submicron channel region. The bias dependence of the extrinsic overlap capacitance is observed to be channel-doping-concentration dependent. >

Recently multilevel flash memory has attracted many developers' attentions. P-channel flash memory has been found to be a promising candidate due to the low-voltage and low-power programming and the ease of scaling-down. Two programming mechanisms: (a) Channel Hot Hole Induced Hot Electron (CHHIHE), and (b) Band-To-Band Tunneling Induced Hot Electron (BTBTIHE) can be used as a high efficient programming method in p-channel rather than in n-channel flash memory. Based upon CHHIHE and BTBTIHE programming, the multilevel applications and analysis of p-channel flash memory are presented. Different engineering guidelines are given for these two programming techniques.

In respect of trench gate power devices, it is difficult to achieve satisfactory gate oxide leakage current, breakdown voltage and reliability characteristics. Trench etching process induced silicon surface damage, convex corner and contamination, which will degrade the silicon dioxide quality. It is convinced that post etching treatment including sacrificial oxidation and chemical dry ashing can improve the gate oxide quality significantly. In this article, we study the treatment of a trench capacitor with sacrificial oxidation and classify the effect of each parameter in the oxidation process. The benefit of N/sub 2/O annealing after gate oxidation will also be discussed. The evaluations of I-V and C-V characteristics are the main considerations of the gate oxide quality in this research.

This work describes the utilization of a novel test structure called addressable failure site test structure for short-loop defect detection and proposed a prototype test structure for SRAM process defect detection in advanced semiconductor manufacturing. The novel test structures are used to identify the locations of killer defects which are then used to wafer map defect sites. This simple and efficient killer defect identification of process steps is employed as yield enhancement strategy.

The dislocation at the trench corner under Poly mask edges was found to be the major killer of junction leakage in generic logic technology. The impact of the sacrificial oxide (SAC-OX) of the well ion implantation (I/I) module and the source/drain (S/D) I/I to the defect formation are investigated for the first time. The influence on N + /P-Well junction leakage caused by the I/I sacrificial oxide from the Rapid Thermal Oxidation (RTO) and Furnace Oxidation (FO) are evaluated by using the process monitoring test structures. Based on the analysis of test structures and the yield evaluation of product, the optimized condition is proposed.

We propose a new Body-Effect-assisted NOR-type (BeNOR) flash memory for multilevel storage application. Body effect assisted self-convergent programming employs secondary electron injection but a different operation bias from the CHannel Initiated Secondary ELectron (CHISEL) flash. Accurately programmed states are accomplished by the linear dependence of VTH on the bit-line voltage; therefore, parallel multilevel programming and elimination or reduction of bit-by-bit verification can be achieved. In this paper, programming power consumption and reliability considerations are also assessed for efficient and long-term operation.

We propose a new Body-Effect-assisted NOR-type (BeNOR) flash memory for multilevel storage application. Body effect assisted self-convergent programming employs secondary electron injection but a different operation bias from the CHannel Initiated Secondary ELectron (CHISEL) flash. Accurately programmed states are accomplished by the linear dependence of V TH on the bit-line voltage; therefore, parallel multilevel programming and elimination or reduction of bit-by-bit verification can be achieved. In this paper, programming power consumption and reliability considerations are also assessed for efficient and long-term operation.

A new trap-assisted band-to-band tunneling (TAB) gate current model is proposed to describe the new observed band-to-band tunneling (BBT) induced gate current characteristics of p-channel metal-oxide-semiconductor field effect transistors (PMOSFET's) with ultra-thin gate oxide. Based on this new TAB gate current model, the off-state gate currents of PMOSFET's with various sub-3 nm gate oxides can be well characterized, while the conventional BBT current model is no longer applicable in this regime.

A new self-convergent constant current programming achieved by a ramp-up source voltage is extensively studied in this work. Based on the results of a constant programming current and self-convergent characteristics, several methods are presented to achieve accurate control of multiple programmed states. Both efficient programming speed and excellent reliability are demonstrated. The proposed programming technique is considered to be a promising candidate for high-speed, high-density, and low-power multilevel split gate flash memory.

In this paper, we propose a new programming technique for multilevel AND-type flash memory. It achieves multiple programmed states through a bit-line-controlled self-convergent operation. Experimental results demonstrate superior capability of tightening threshold voltage distribution and significant improvement in endurance characteristics. Excellent immunity to program disturbance is also demonstrated.

A new NAND-type electrical erasable programmable read only memory (EEPROM), which employs (1) the novel in-cell temporary storage (ICTS) technique and (2) the novel multiple-wordline parallel programming (MWPP) method, is proposed to reduce the unit cell size and decrease the overall programming time. The ICTS approach latches input data directly to the selected EEPROM cells by an inverted channel with different input bitline voltages. After all the selected cells are latched to individual data, the MWPP method simultaneously raises all selected wordlines to high voltage to perform FN tunneling for parallel programming. The equivalent byte programming time is considerably reduced by employing parallel programming. The high-speed and high-density features further reduce the EEPROM testing cost for manufacturers and save programming time and cost for system providers.

We propose a novel operation scheme for multilevel p-channel flash memory cell with a self-convergent programming process. By utilizing the simultaneous Fowler-Nordheim electron tunneling out of floating gate and channel hot electron injection into floating gate, the threshold voltage of memory cell can be converged to a specific value. The gate pulse level can be varied to result in different converged threshold voltages such that multilevel can be achieved. Owing to the nature of self-convergence, the possibility of eliminating or reducing the verification operation in multilevel applications increases considerably by using the proposed scheme. In this study the reliability considerations of this programming technique for long-term operations are also addressed.

A new self-convergent programming method for multilevel AND-type flash memory is described to accurately control the dispersion of the programmed threshold voltage which is caused by the deviation of the applied voltage or the FN tunneling current. Both channel initiated secondary electron injection (CHISEL) and avalanche hot electron injection (AHEI) following the edge FN electron ejection can be used as the self-convergent programming techniques. However, CHISEL is shown to be better than AHEI for self-convergent operation due to faster speed, lower voltage, lower power consumption, and better oxide reliability.

A volatile memory structure with nanocrystalline Si (nc-Si) layer and auxiliary floating polysilicon gate is proposed. The charges are injected through tunnel oxide and nc-Si layer by Fowler-Nordheim (F-N) tunneling and then stored in the stacked structure. The nc-Si layer improves programming speed during F-N operation and the extended structure with floating gate improves the limited charge storage volume and makes the memory device with distinct threshold voltage window. The reliability of this cell is shown to be sufficient for using as dynamic memory.

It is found that the thermal stability of CoSi2 films is improved by N2 + implantation (I/I) because the grain size of CoSi2 films with N2 + I/I is much smaller than that without N2 + I/I. Rutherford backscattering spectrometry (RBS) and Auger electron spectroscopy (AES) analyses show that the nucleation of CoSi2 transformation from CoSi is suppressed by N2 + I/I. The nucleation temperature for the sample with 5×1015 cm-2 N2 + I/I is about 25°C higher than that without N2 + I/I. Since the nucleation temperature is increased, CoSi2 films are formed incompletely at the as-formed state; thus, CoSi2 has small grain size. As a result, the thermal stability of CoSi2 films is significantly improved by N2 + I/I due to the small grain size of CoSi2.

This paper describes and discusses intensively the charge loss characteristics in the stacked-gate memory device with interpoly oxide-nitride-oxide (ONO) dielectric at elevated temperatures. There exist two distinct phases in the charge loss characteristics. The dominant mechanism in the first phase can be described as the charge transport in the nitride layer. The second phase is dominated by effective thermionic emission effect from the stacked gate system. A linearly proportional relationship is also observed between normalized charge loss in the first phase and initial threshold voltage shift. Due to the fast charge loss rate, the charge loss in the first phase governs the threshold instability of the stacked-gate device. A method to determine the programming window for better threshold voltage stability based on charge loss in first phase is proposed.

In this paper, the n-channel Flash memory device degradation by utilizing the drain-avalanche hot electron (DAHE) self-convergence (S-C) scheme is demonstrated for the first time. The injected hole originated by the channel electron induced avalanche hot hole generation is believed to be responsible for this degradation. This hole injection phenomena not only result in the interface state generation but also lead to the hole trapping in the tunnel oxide. The increased interface states degrade the conduction of the channel current severely, which leads to abnormal write/erase (W/E) endurance characteristics. The trapped holes in the tunnel oxide increase the tunneling probability and cause the gate disturbance issue. From the concerns of long term reliability, the self-convergence operation by utilizing the DAHE mechanism is not a proper scheme for reliable Flash memory products.

A new technique of determining the effective channel length by directly measuring source-drain series resistance of metal-oxide-semiconductor field-effect transistors (MOSFETs) was proposed. By using MOSFETs with scaled gate lengths, the source-drain series resistance can be obtained from a device whose source and drain regions are connected. In order to determine whether a MOSFET's source and drain are connected, a `difference of total resistance' (DTR) method, which can also be used to electrically determine the gate length of a normal MOSFET after the fabrication process, was developed in this study. The effective channel length can then be extracted from the obtained series resistance and I–V of MOSFETs. This technique, although it requires very short-gate-length devices, is not affected by source-drain series-resistance gate bias dependence issue encountered in conventional I–V methods.

In this paper, the effects of large-tilted-angle p-pocket (LAP) implantation on the performance and reliability of stacked-gate memory cell are investigated. The utilization of LAP process achieves the improved programming efficiency and reduced punchthrough susceptibility. The 45° LAP cell featuring a fastest programming speed, however, would not be desirable due to the seriously aggravated read current degradation, drain/read disturbance, and early snap-back breakdown. The cells with 0° and 30° tilted angle are the feasible cells with the moderate programming performance and acceptable reliability constraints. Furthermore, the 0° LAP cell is preferred for the fact that it exhibits the desirable read current than that in 30° cell. Based on the cell performance and reliability consideration, the 0° p-pocket implanted cell is the optimal angle among 0°, 30° and 45° for the future scaling of stacked-gate memory cell.

Thin silicon-rich-oxide (SRO) film can be an efficient and reliable tunneling injector for the low voltage application in Flash memory cell. To date, no work has been done on the quantitative and microscopical tunneling model for the SRO enhancement behavior. Moreover, no complete investigation on array-level SRO Flash cell have been presented. In this paper, a new low voltage SNAND (SRO NAND) cell is proposed and investigated, especially in term of performance characteristics and reliability issues. Furthermore, a two-dimensional microscopical model for SRO tunneling characteristics is developed to quantitatively explain the tunneling enhancement characteristics for SRO Flash memory cell. Results show that the tunneling model agrees well with the tunneling characteristics of SNAND cell and also provided the insight into tunnel oxide scaling in SNAND cell operation. The erase and program voltage can be reduced from 22 V to 7 V and 12 V with improved erase speed up to 2 orders, respectively. More than 105 endurance cycles are achieved. The feasibility of the SNAND cell is demonstrated.

The gate oxide integrity degradation due to the thermal instability of cobalt silicide ( CoSi2) in p-type polysilicon gate metal-oxide-semiconductor (MOS) capacitors is alleviated by arsenic implantation into p-type poly-Si gate. The thin gate oxides of p+-poly MOSFETs were severely degraded due to agglomeration of cobalt silicide at high temperature after silicidation. The degradation of thin gate oxide was found to be suppressed by the implantion of arsenic into p-type polysilicon gate. This is due to the fact that arsenic atoms segregate simultaneously into grain boundary and interface, and diffusion of decomposed cobalt along grain boundary was then retarded during agglomeration.

A novel method for suppressing boron-penetration is reported. Antimony co-implantation with BF2 in p-poly gate of metal-oxide-semiconductor (MOS) device is found to effectively alleviate the boron-penetration enhanced by the existence of fluorine. The boron-penetration in BF2 implanted poly-gate is observed to be significantly reduced as the dose of co-implanted antimony increases. From Fourier transform infrared spectroscopy (FTIR) and X-ray photoelectron spectroscopy (XPS) analysis, the suppression of boron-penetration is shown to be possibly due to the formation of Sb-F compound, which reduces the fluorine enhanced boron diffusion.

A non-destructive high resolution “Decoupled C-V Technique” for small geometry devices has been developed and demonstrated to successfully extract the intrinsic channel capacitance of submicron metal-oxide-semiconductor field effect transistors (MOSFET's). The effective channel doping concentration calculated from the extracted intrinsic gate capacitance presents an obvious dopant concentration enhancement in the intrinsic channel region of submicron devices compared to that of long channel devices, as the channel implant dose increases beyond a critical value. The anomalous reverse short channel effect i.e. threshold voltage increases with channel length scaled down, is simultaneously observed on the heavily doped short channel devices. The self-consistency between the C-V and I-V measurement supports that the reverse short channel effect apparent in the submicron CMOS technology is due to the channel dopant enhancement induced by high dose channel implants for both N-channel and P-channel devices.

Hydrogenation kinetics of the aluminum and boron acceptors in oxidized silicon have been obtained during constant current avalanche electron injection stress in contrast to constant voltage stress reported previously by us. The annealing kinetics have been measured at eight new temperatures for Al‐doped metal–oxide–semiconductor capacitors over the range 120–205 °C. Four phases were observed during the thermal activation of the aluminum acceptor. The first phase consisted of an initial drop of the hole concentration. Phase two was associated with the first‐order hydrogen‐acceptor bond‐breaking reaction. The last two phases were attributed to the second‐order kinetics of the hydrogen molecule formation and breakup reaction. The thermal activation energy for the aluminum acceptor was 1.6 eV in contrast to our previous 2.2 eV based on fewer (three) annealing temperatures, giving more firmly the chemical trend, B(1.1 eV)