135 results on '"Chante, J.P."'
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2. Electrical characterization of silicon carbide n+pp+ diodes with an N-implanted n+ emitter
3. Surface effects on current mechanisms in 6 H-SiC n+pp+ structures passivated with a deposited oxide
4. Effect of boron diffusion on the high-voltage behavior of 6H-SiC p+nn+ structures
5. State variable modeling of the power pin diode using an explicit approximation of semiconductor device equations: a novel approach
6. Annealing studies of Al-implanted 6H-SiC in an induction furnace
7. Study of 6H–SiC high voltage bipolar diodes under reverse biases
8. Experimental characterization of a 4H–SiC high voltage current limiting device
9. An improved technology of 6H-SiC power diodes
10. Numerical investigation for a Grounded Gate NMOS Transistor under electrostatic discharge (ESD) through TLP method
11. Lift-off technology for SiC UV detectors
12. Electrical characteristics modeling of large area boron: compensated 6H-SiC pn structures
13. A current conveyor-based high-frequency analog switch
14. Temperature behavior of the 6H-SiC pn diodes
15. Current–voltage characteristics of large area 6H-SiC pin diodes
16. On the interpretation of high frequency capacitance data of 6H-SiC boron compensated pin junction
17. P–N Junction creation in 6H-SiC by aluminum implantation
18. Design of a 600 V silicon carbide vertical power MOSFET
19. Surface effects on current mechanisms in 6H-SiC n+pp+ structures passivated with a deposited...
20. C.A.D. OF THE PERIPHERY OF PLANAR JUNCTIONS
21. A comparative study of high temperature aluminium post implantation annealing in 6H and 4hsic, non-uniformity temperature effects
22. 6H-SiC diodes with cellular structure to avoid micropipe effects
23. A 4H-SiC high-power-density VJFET as controlled current limiter
24. ESD evaluation of a low voltage triggering SCR (LVTSCR) device submitted to transmission line pulse (TLP) test
25. Very low RON measured on 4H-SiC accu-MOSFET high power device.
26. Human Body Model test of a Low Voltage Threshold SCR device: Simulation and comparison with the Transmission Line Pulse test.
27. Electrical and electrothermal 2D simulations of a 4H-SiC high voltage current limiting device for serial protection applications.
28. Electrothermal modeling of IGBTs: application to short-circuit conditions
29. Characterisation of deep level trap centres in 6H-SiC p-n junction diodes
30. Study on dv/dt Susceptibility of a MCT Under Low Control Voltage
31. An attempt to explain thermally induced soft failures during low level ESD stresses: study of the differences between soft and hard NMOS failures
32. Periphery protection for silicon carbide devices: state of the art and simulation
33. Montecarlo simulation of ion implantation into SiC-6H single crystal including channeling effect
34. An Attempt To Explain Thermally Induced Soft Failures During Low Level Esd Stresses: Study Of The Differences Between Soft And Hard Nmos Failures.
35. Design considerations of a MOS-bipolar Darlington structure: The vertical insulated base transistor (IBT)
36. Semiconductor Materials for High Temperature Power Devices
37. Investigation of Temperature Effects on Fast Gold Doped High Voltage Rectifiers
38. Turn-off analysis of the IGBT used in ZCS mode.
39. A New Analytical Model of CMOS Latch-up.
40. Investigations on the thermal behavior of interconnects under ESD transients using a simplified thermal RC network.
41. Characterization of deep levels in 6H-SiC pn junction diodes.
42. Study of a 3D phenomenon during ESD stresses in deep submicron CMOS technologies using photon emission tool.
43. SIMULATION OF BIPOLAR TRANSPORT IN SEMICONDUCTOR P‐N JUNCTIONS USING THE GENERALIZED HYDRODYNAMIC EQUATIONS
44. Carrier lifetime measurement by ramp recovery of p-i-n diodes
45. New method of measuring the internal current gain of a transistor using avalanche multiplication.
46. Local bipolar-transistor gain measurement for VLSI devices.
47. Investigations on the thermal behavior of interconnects under ESD transients using a simplified thermal RC network
48. Analytical expression for the potential of guard rings of diodes operating in the punchthrough mode.
49. Electric measurement and modelling of the emitter base junction behaviour of VLSI silicon transistor
50. Improvement of on-resistance of MOS-gated devices
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