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The design, materials, process, and fabrication of a hybrid substrate for the heterogeneous integration of chips with 50μm-pitch (minimum) by fan-out chip-last panel-level packaging are presented. The hybrid substrate consists of a fine metal linewidth (L), spacing (S), and thickness (H) RDL (redistribution-layer) substrate, solder joints with underfill, and a build-up package substrate. The dielectric material for the fine metal L/S/H RDL-substrate is an Ajinomoto build-up film (ABF).

In this study, the reliability of chiplets heterogeneous integration on a 2.3D hybrid substrate using solder joint and underfill is investigated. Emphasis is placed on the thermal cycling test and drop test of the structure. The test results are plotted into Weibull distributions, where the Weibull slope and characteristic life at median rank are presented. At 90% confidence, the true Weibull slope interval and the true characteristic life interval are also provided. A linear acceleration factor is adopted to map the solder joint reliability at test condition to the solder joint reliability at an operating condition. The failure location and failure mode of the chip/package assembly of the heterogeneous integration package are provided and discussed.

The panel-level redistribution-layer (RDL)-first fan-out packaging for hybrid substrate is studied. Emphasis is placed on the process, materials, design, and fabrication of: 1) heterogeneous integration of one large chip and one small chip with 50- $\mu \text{m}$ pitch (minimum); 2) fine metal linewidth and spacing RDL-first substrate on a temporary panel carrier; 3) ordinary build-up package substrate on a panel; 4) hybrid substrate which is by soldering the RDL-first substrate on the build-up substrate; and 5) chips to hybrid substrate bonding and underfilling. Reliability assessment by thermomechanical simulation includes thermal cycling of the heterogeneous integration of the two-chip package on the hybrid substrate that is performed by a nonlinear temperature- and time-dependent finite-element analysis.

The fan-out panel-level chip-last packaging for heterogeneous integration is investigated. Emphasis is placed on the design, materials, process, and fabrication of: (a) the heterogeneous integration of one large chip and one small chip with 50µm-pitch (minimum), (b) a fine metal linewidth (L) and spacing (S) redistribution-layer (RDL)-first substrate on a temporary glass carrier, (c) an ordinary build-up package substrate on a panel, (d) a hybrid substrate which is by soldering the RDL-substrate on top of the build-up substrate, and (e) the chips to hybrid substrate bonding and underfilling. Reliability assessment by thermomechanical simulation includes thermal cycling of the heterogeneous integration of the two-chip package on the hybrid substrate that is performed by a nonlinear temperature- and time-dependent finite-element analysis.