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The simulation and design of electronic devices such as transistors is vital for the semiconductor industry. Conventionally, a device is intuitively designed and simulated using model equations, which is a time-consuming and expensive process. However, recent machine learning approaches provide an unprecedented opportunity to improve these tasks by training the underlying relationships between the device design and the specifications derived from the extensively accumulated simulation data. This study implements various machine learning approaches for the simulation acceleration and inverse-design problems of fin field-effect transistors. In comparison to traditional simulators, the proposed neural network model demonstrated almost equivalent results (R2 = 0.99) and was more than 122,000 times faster in simulation. Moreover, the proposed inverse-design model successfully generated design parameters that satisfied the desired target specifications with high accuracies (R2 = 0.96). Overall, the results demonstrated that the proposed machine learning models aided in achieving efficient solutions for the simulation and design problems pertaining to electronic devices. Thus, the proposed approach can be further extended to more complex devices and other vital processes in the semiconductor industry.

There is a growing consensus that the physics-based model needs to be coupled with machine learning (ML) model relying on data or vice versa in order to fully exploit their combined strengths to address scientific or engineering problems that cannot be solved separately. We propose several methodologies of bridging technology computer-aided design (TCAD) simulation and artificial intelligence (AI) with its application to the tasks for which traditional TCAD faces challenges in terms of simulation runtime, coverage, and so on. AI-emulator that learns fine-grained information from rigorous TCAD enables simulation of process technologies and device in real-time as well as large-scale simulation such as full-pattern analysis of stress without high demand on computational resource. To accelerate atomistic molecular dynamics (MD) simulation, we have done a comparison study of descriptor-based and graph-based neural net potential, and also show their capability with large-scale and long-time simulation of silicon oxidation. Finally, we discuss the use of hybrid modeling of AI- and physics-based model for the case where physical equations are either fully or partially unknown.

The artificial neural network (ANN)-based compact modeling methodology is evaluated in the context of advanced field-effect transistor (FET) modeling for Design-Technology-Cooptimization (DTCO) and pathfinding activities. An ANN model architecture for FETs is introduced, and the results clearly show that by carefully choosing the conversion functions (i.e., from ANN outputs to device terminal currents or charges) and the loss functions for ANN training, ANN models can reproduce the current–voltage and charge–voltage characteristics of advanced FETs with excellent accuracy. A few key techniques are introduced in this work to enhance the capabilities of ANN models (e.g., model retargeting, variability modeling) and to improve ANN training efficiency and SPICE simulation turn-around-time (TAT). A systematical study on the impact of the ANN size on ANN model accuracy and SPICE simulation TAT is conducted, and an automated flow for generating optimum ANN models is proposed. The findings in this work suggest that the ANN-based methodology can be a promising compact modeling solution for advanced DTCO and pathfinding activities.

This paper presents a deep neural network based test vector generation method for dynamic verification of memory devices. The proposed method is built on reinforcement learning framework, where the action is input stimulus on device pins and the reward is coverage score of target circuitry. The developed agent efficiently explores high-dimensional and large action space by using policy gradient method with A-nearest neighbor search, transfer learning, and replay buffer. The generated test vectors attained the coverage score of 100% for fifteen representative circuit blocks of modern DRAM design. The output vector length was only 7% of the human-created vector length.

This paper presents a novel approach to enable real-time device simulation and optimization. State-of-the-art algorithms which can describe semiconductor domain are adopted to train deep learning models whose input and output are process condition and doping profile / electrical characteristic, respectively. Our framework enables to update automatically deep learning models by estimating the uncertainty of the model prediction. Our Real-Time TCAD framework is validated on 130nm processes for display driver integration circuit (DDI), and 1) prediction time was 530,000 times faster than conventional TCAD, and time spent for process optimization was reduced by 300,000 times compared to human expert, 2) the model achieved average accuracy of 99% compared to TCAD simulation results, and thus, 3) process development time for DDI was reduced by 8 weeks.

Although transparent conductive oxides such as indium tin oxide (ITO) are widely employed as transparent conducting electrodes (TCEs) for applications such as touch screens and displays, new nanostructured TCEs are of interest for future applications, including emerging transparent and flexible electronics. A number of twodimensional networks of nanostructured elements have been reported, including metallic nanowire networks consisting of silver nanowires, metallic carbon nanotubes (m-CNTs), copper nanowires or gold nanowires, and metallic mesh structures. In these single-component systems, it has generally been difficult to achieve sheet resistances that are comparable to ITO at a given broadband optical transparency. A relatively new third category of TCEs consisting of networks of 1D-1D and 1D-2D nanocomposites (such as silver nanowires and CNTs, silver nanowires and polycrystalline graphene, silver nanowires and reduced graphene oxide) have demonstrated TCE performance comparable to, or better than, ITO. In such hybrid networks, copercolation between the two components can lead to relatively low sheet resistances at nanowire densities corresponding to high optical transmittance. This review provides an overview of reported hybrid networks, including a comparison of the performance regimes achievable with those of ITO and single-component nanostructured networks. The performance is compared to that expected from bulk thin films and analyzed in terms of the copercolation model. In addition, performance characteristics relevant for flexible and transparent applications are discussed. The new TCEs are promising, but significant work must be done to ensure earth abundance, stability, and reliability so that they can eventually replace traditional ITO-based transparent conductors.

The optimal position of dislocation stress memorization technique (DSMT) to maximize n-FinFET performance as well as the stacking fault (SF) number, [Ge] concentration limit and p-FinFET DC tradeoff in eSiGe are newly investigated by using the scanning moire fringe (SMF) and scanning transmission electron microscopy-geometrical phase analysis (STEM-GPA) validated in-house 3D TCAD model in various bulk finFET structures.

Transparent conducting electrodes (TCEs) require high transparency and low sheet resistance for applications in photovoltaics, photodetectors, flat panel displays, touch screen devices and imagers. Indium tin oxide (ITO), or other transparent conductive oxides, have typically been used, and provide a baseline sheet resistance (RS) vs. transparency (T) relationship. However, ITO is relatively expensive (due to limited abundance of Indium), brittle, unstable, and inflexible; moreover, ITO transparency drops rapidly for wavelengths above 1000 nm. Motivated by a need for transparent conductors with comparable (or better) RS at a given T, as well as flexible structures, several alternative material systems have been investigated. Single-layer graphene (SLG) or few-layer graphene provide sufficiently high transparency (≈97% per layer) to be a potential replacement for ITO. However, large-area synthesis approaches, including chemical vapor deposition (CVD), typically yield films with relatively high sheet resistance due to small grain sizes and high-resistance grain boundaries (HGBs). In this paper, we report a hybrid structure employing a CVD SLG film and a network of silver nanowires (AgNWs): RS as low as 22 Ω/□ (stabilized to 13 Ω/□ after 4 months) have been observed at high transparency (88% at λ = 550 nm) in hybrid structures employing relatively low-cost commercial graphene with a starting RS of 770 Ω/□. This sheet resistance is superior to typical reported values for ITO, comparable to the best reported TCEs employing graphene and/or random nanowire networks, and the film properties exhibit impressive stability under mechanical pressure, mechanical bending and over time. The design is inspired by the theory of a co-percolating network where conduction bottlenecks of a 2D film (e.g., SLG, MoS2) are circumvented by a 1D network (e.g., AgNWs, CNTs) and vice versa. The development of these high-performance hybrid structures provides a route towards robust, scalable and low-cost approaches for realizing high-performance TCE.

The feasibility of medium-high fraction SiGe based FinFET pMOS devices for a sub-10nm CMOS logic technology from a performance (I EFF @ fixed I OFF ) standpoint is evaluated, considering three key device aspects — stress, band-to-band-tunneling (BTBT), and interface charge density (DIT). The analysis reveals that while for high Ge (>90%), performance is limited by BTBT, overall stress reduction beyond Ge 65% further limits performance. Including realistic (DIT) profile further shows that optimum Ge content is between 40%∼50% for low power applications.

Traditional transparent conducting materials such as ITO are expensive, brittle, and inflexible. Although alternatives like networks of carbon nanotubes, polycrystalline graphene, and metallic nanowires have been pro- posed, the transparency-conductivity trade-off of these materials makes them inappropriate for broad range of applications. In this paper, we show that the conductivity of polycrystalline graphene is limited by high resistance grain boundaries. We demonstrate that a composite based on polycrystalline graphene and as ubpercolating network of metallic nanowires offers as imple and effective route to reduced resistance while maintaining high transmittance. This new approach of "percolation-doping by nanowires" has the potential to beat the transparency- conductivity constraints of existing materials and may be suitable for broad applications in photovoltaics, flexible electronics, and displays.

In this paper, we address the question of how to engineer the electronic structure to enhance the performance of a thermoelectric material. We examine several different materials and show that all of them, even those for which giant Seebeck coefficients have been predicted, display a value that is expected from conventional thermoelectric theory. For molecular thermoelectrics, we show that the detailed lineshape plays an important role. Finally, using III–V alloy semiconductors as a model system, we explore the role of electronic structure in the Seebeck coefficient, electrical conductivity, and power factor. In the process, some general guidelines for engineering the electronic component of thermoelectric performance are identified.

Investigating of ON-current boosting, short channel effect (SCE), and self-heating effect in Si pFinFET on a SiC stress relaxed buffer (SRB) layer is presented compared with SiGe pFinFET on a SiGe-SRB. Both SiC-SRB-based device and SiGe-SRB-based device show mobility boosting due to high compressive channel stress as well as enhanced SCE due to significant suppressing of subfin leakage. However, if self-heating is considered, SiGe-based devices exhibit non-negligible current degradation compared to SiC-SRB-based devices. Even though SiGe channel devices on a SiGe-SRB show better performance compared with SiC-SRB-based device, it is shown that the impact of BEOL reliability should be considered carefully.

The DC current-voltage characteristics of an n-channel silicon MOSFET with an effective gate length of about 60 nm are analyzed and interpreted in terms of scattering theory. The experimental results are found to be consistent with the predictions of scattering theory - the drain current is closer to the ballistic limit under high drain bias than under low drain bias, and the on-current in strong inversion is limited by a small portion of the channel near the source. The question of how the low- and high- V DS drain currents are related to the near-equilibrium, long-channel mobility is also addressed. In the process of this analysis, theoretical and experimental uncertainties that make it difficult to extract numerically precise values of the scattering parameters are identified.

For devices beyond the 14nm node, it is important to investigate performance boosters such as high mobility channels. Although pure Ge offers a higher hole mobility than Si, conventional problems like surface passivation and its integration with Si makes SiGe alloy with low Ge mole fraction a viable option. The significance of alloy scattering, however, has been widely debated [1-3], so the accurate modeling of alloy scattering in SiGe channel has become an important issue to predict the performance of future SiGe-based FETs. Usually, the calculation of alloy scattering mobility assumes an alloy scattering center in a simple analytical form with some fitting parameters, which is a good practical approach but has a limited predictability. In this paper, an atomistic tight-binding simulation is used to study alloy scattering in SiGe-based FETs, and to compare with experimental data. We conclude (i) although it is essentially impossible to avoid alloy scattering in SiGe material, (ii) high-mobility is indeed achieved in SiGe channel by combining lattice-mismatch stresses from Si virtual substrate with stresses from Source/Drain(SD) stressor.

Single layer graphene (SLG), with high optical transparency and electrical conductivity, may potentially be used as flexible transparent electrode in photovoltaics, photo detectors, and flat panel displays. While its optical transmittance exceeds 95% (significantly better than most traditional materials), its sheet resistance (ρ poly-G ) must be reduced below 10–20Ω/□ for viable replacement of present Transparent Conducting Oxides (TCOs) like Indium doped Tin Oxide (ITO). However, large scale CVD SLG is typically polycrystalline, consisting of many grains, with neighboring grains separated by high- and low-resistance grain boundaries (HGB and LGB), see Fig. 1 and 7. The HGBs severely limit the (percolating) electronic transport, so that ρ poly-G > 1000Ω/□. It is therefore important to determine the electronic nature and fraction of HGB to improve transport in polycrystalline SLG.

The question of what bandstructure produces the best thermoelectric device performance is revisited from a Landauer perspective. We find that a delta-function transport distribution function (TDF) results in operation at the Mahan-Sofo upper limit for the thermoelectric figure-of-merit, ZT. We show, however, the Mahan-Sofo upper limit itself depends on the bandwidth (BW) of the dispersion, and therefore, a finite BW dispersion produces a higher ZT when the lattice thermal conductivity is finite. Including a realistic model for scattering profoundly changes the results. Instead of a narrow band, we find that a broad BW is best. The prospects of increasing ZT through high valley degeneracy or by distorting the density-of-states are discussed from a Landauer perspective. We conclude that while there is no simple answer to the question of what bandstructure produces the best thermoelectric performance, the important considerations can be expressed in terms of three parameters derived from the bandstructure-the density-of-states, D(E), the number of channels, M(E), and the mean-free-path, lambda(E). (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4727855]

The question of what fraction of the total heat flow is transported by phonons with different mean-free-paths is addressed using a Landauer approach with a full dispersion description of phonons to evaluate the thermal conductivities of bulk and thin film silicon. For bulk Si, the results reproduce those of a recent molecular dynamic treatment showing that about 50% of the heat conduction is carried by phonons with a mean-free-path greater than about 1 mu m. For the in-plane thermal conductivity of thin Si films, we find that about 50% of the heat is carried by phonons with mean-free-paths shorter than in the bulk. When the film thickness is smaller than similar to 0.2 mu m, 50% of the heat is carried by phonons with mean-free-paths longer than the film thickness. The cross-plane thermal conductivity of thin-films, where quasi-ballistic phonon transport becomes important, is also examined. For ballistic transport, the results reduce to the well-known Casimir limit [H. B. G. Casimir, Physica 5, 495-500 (1938)]. These results shed light on phonon transport in bulk and thin-film silicon and demonstrate that the Landauer approach provides a relatively simple but accurate technique to treat phonon transport from the ballistic to diffusive regimes. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4710993]

Using a full dispersion description of phonons, the thermal conductivities of bulk Si and Bi(2)Te(3) are evaluated using a Landauer approach and related to the conventional approach based on the Boltzmann transport equation. A procedure to extract a well-defined average phonon mean-free-path from the measured thermal conductivity and given phonon-dispersion is presented. The extracted mean-free-path has strong physical significance and differs greatly from simple estimates. The use of simplified dispersion models for phonons is discussed, and it is shown that two different Debye temperatures must be used to treat the specific heat and thermal conductivity (analogous to the two different effective masses needed to describe the electron density and conductivity). A simple technique to extract these two Debye temperatures is presented and the limitations of the method are discussed. (C) 2011 American Institute of Physics. [doi:10.1063/1.3567111]

We use a state-of-the-art non-equilibrium quantum transport simulation code, NEMO-1D, to address the device physics and performance benchmarking of cross-plane superlattice Peltier coolers. Our findings show quantitatively how barriers in cross-plane superlattices degrade the electrical performance, i.e. power factor. The performance of an In0.53Ga0.47As/In0.52Al0.48As cross-plane SL Peltier cooler is lower than that of either a bulk In0.53Ga0.47As or bulk In0.52Al0.48As device, mainly due to quantum mechanical effects. We find that a cross-plane SL device has a Seebeck coefficient vs. conductance tradeoff that is no better than that of a bulk device. The effects of tunneling and phase coherence between multi barriers are examined. It is shown that tunneling, SL contacts, and coherency only produce oscillatory behavior of Seebeck coefficient vs. conductance without a significant gain in PF. The overall TE device performance is, therefore, a compromise between the enhanced Seebeck coefficient and degraded conductance.

The Landauer approach provides a conceptually simple way to calculate the intrinsic thermoelectric (TE) parameters of materials from the ballistic to the diffusive transport regime. This method relies on the calculation of the number of propagating modes and the scattering rate for each mode. The modes are calculated from the energy dispersion (E(k)) of the materials which require heavy computation and often supply energy relation on sparse momentum (k) grids. Here an efficient method to calculate the distribution of modes (DOM) from a given E(k) relationship is presented. The main features of this algorithm are, (i) its ability to work on sparse dispersion data, and (ii) creation of an energy grid for the DOM that is almost independent of the dispersion data therefore allowing for efficient and fast calculation of TE parameters. The inclusion of scattering effects is also straight forward. The effect of k-grid sparsity on the compute time for DOM and on the sensitivity of the calculated TE results are provided. The algorithm calculates the TE parameters within 5% accuracy when the K-grid sparsity is increased up to 60% for all the dimensions (3D, 2D and 1D). The time taken for the DOM calculation is strongly influenced by the transverse K density (K perpendicular to transport direction) but is almost independent of the transport K density (along the transport direction). The DOM and TE results from the algorithm are bench-marked with, (i) analytical calculations for parabolic bands, and (ii) realistic electronic and phonon results for $Bi_{2}Te_{3}$., Comment: 16 Figures, 3 Tables, submitted to Journal of Computational electronics

The question of whether relaxing momentum conservation can increase the performance of thermionic cooling device is examined. Both homojunctions and heterojunctions are considered. It is shown that for many cases, a non-conserved lateral momentum model overestimates the current. For the case of heterojunctions with a much heavier effective mass in the barrier and with a low barrier height, however, non-conservation of lateral momentum may increase the current. These results may be simply understood from the general principle that the current is limited by the location, well or barrier, with the smallest number of conducting channels. These results also show that within thermionic emission framework, the possibilities of increasing thermionic cooling by relaxing momentum conservation are limited. More generally, however, when the connection to the source is weak or in the presence of scattering, the situation may be different. Issues that deserve further study are identified., 36 pages, 1 table, 9 figures

Highly manufacturable 64Mbit PRAM has been successfully fabricated using N-doped Ge/sub 2/Sb/sub 2/Te/sub 5/ (GST) and optimal GST etching process. Using those technologies, it was possible to achieve the low writing current of 0.6 mA and clear separation between SET and RESET resistance distributions. The 64Mb PRAM was designed to support commercial NOR flash memory compatible interfaces. Therefore, the fabricated chip was tested under the mobile application platform and its functionality and reliability has been evaluated by operation temperature dependency, disturbance, endurance, and retention. Finally, it was clearly demonstrated that high density PRAM can be fabricated in the product level with strong reliability to produce new nonvolatile memory markets.

PRAM(Phase-Change RAM) is a promising memory that can solve the problems of conventional memory and has the nearly ideal memory characteristics. We reviewed the issues for high density PRAM integration. Writing current reduction is the most urgent problem for high density PRAM realization. We presented process factors which affect the writing current and the result of improvement. Finally we demonstrated results of 64Mb PRAM integration based on 0.18/spl mu/m CMOS technology.

We have integrated a 64Mb nonvolatile random access memory using phase transition phenomena. Based on 0.18/spl mu/m-CMOS technologies, the vertical contact typed memory cell is fabricated. The device density can be sharply increased with decreasing the writing current and the GST size. But for reduction of writing current, issues including set and interface resistances should be stabilized. Additionally, our results also show the feasibility of 256Mb nonvolatile PRAM with writing time below 100ns.