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Gallium Nitride (GaN) high-electron mobility transistors (HEMTs) are highly promising for high-frequency and high-power applications due to their superior properties, such as a wide energy bandgap and high carrier density. The performance of GaN HEMTs is significantly influenced by the interfacial states of the AlGaN barrier, and gate annealing has emerged as a key process for reducing leakage currents and enhancing DC/RF characteristics. This research investigates the impact of gate annealing on AlGaN/GaN HEMTs, focusing on two main aspects: leakage current reduction and improvements in DC and RF efficiency. Through comprehensive electrical analysis, including DC and RF measurements, the effects of gate annealing were experimentally evaluated. The results show a significant reduction in gate leakage current and noticeable improvements in DC/RF performance for the devices that underwent gate annealing. The study confirms that the annealing process can effectively enhance device performance by modifying the material properties at the gate interface. [ABSTRACT FROM AUTHOR]

In this study, the (001) β-Ga2O3 surface was dry etched employing the inductively coupled plasma-reactive ion etching (ICP-RIE) system, and Au/Ni/β-Ga2O3 Schottky barrier diodes (SBDs) were fabricated on the etched surface. The impact of ion bombardment on the (001) β-Ga2O3 surface during dry etching and its effect on current-voltage (I–V) characteristics and breakdown voltage was investigated. The forward current at higher bias decreased with increasing temperature due to the fact that the higher temperatures cause them to be less mobile owing to the scattering effects that reduce the on-current. The temperature-dependent I–V characterization of the Au/Ni/β-Ga2O3 SBD revealed a strong temperature dependence of barrier height and ideality factor associated with the barrier height inhomogeneity at the interface between Ni and β-Ga2O3. Analysis of the barrier height inhomogeneities with the assumption of Gaussian distribution of barrier heights confirmed the presence of a double Gaussian barrier distribution having mean barrier heights of 0.71 and 1.21 eV in the temperature range of (83–158) and (183–283 K), respectively. The Richardson constant value obtained from the modified Richardson plot interpreted with the consideration of Gaussian distribution of barrier heights closely matched with the theoretical value of β-Ga2O3. The fabricated Au/Ni/β-Ga2O3 SBD showed consistent breakdown voltage in the range of 670–695 V over repeated measurements with a time interval of 1 min without exhibiting any damage. However, after an initial breakdown voltage measurement, repeating the measurement with a 30 s interval led to an exponential increase in current, leading to the destruction of the device, associated with the low thermal conductivity of the substrate. The results obtained reveal that the ICP-RIE dry etching did not cause significant damage to the surface. [ABSTRACT FROM AUTHOR]

The authors propose criteria for recess etching to fabricate T‐gate used in InGaAs high electron mobility transistors (HEMTs). By patterning additional rectangular pads on the source and drain metals in the e‐beam lithography step, it is possible to measure the drain‐to‐source resistance (Rds) and current (Ids). The ratio (Γ) of before and after etching for each Rds and Ids can be used as criteria to determine the point in time to stop etching. By performing recess etching with Γ= 1.97 for Rds and Γ= 0.38 for Ids on an epiwafer having cap doping concentration of 2 × 1019 cm−3 and channel indium content of 0.7, the authors have fabricated InGaAs metamorphic high electron mobility transistor (mHEMT) device showing gm,max= 1603 mS/mm and ft= 290 GHz at Lg= 124 nm. The criteria presented can be applied to InGaAs HEMTs with various epitaxial structures. [ABSTRACT FROM AUTHOR]