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In this paper, an improved voltage-mode constant on-time (COT) control DC–DC buck converter is designed, which makes the DC–DC buck converter have good stability. Firstly, an improved compensation scheme is introduced through the analysis and derivation of the traditional voltage-mode COT controlled buck converter model. Then, according to the application requirements of the design, Simplis software modeling is used to verify the correctness of the theoretical analysis. The 0.13 μ m BCD technology is used to tape out the DC–DC converter of the improved voltage mode COT. The input voltage is 3.7–5.5 V and the output voltage is 3.3 V. The chip test mainly includes heavy-load condition in CCM operation, light-load condition in DCM operation, and load transient response. The test results show that the chip can remain stable under heavy-load and light-load conditions. The overshoot and undershoot in transient response can be quickly restored to steady state during the recovery process. Finally, compared with chips of the same type, it shows that the DC–DC chip for portable electronic equipment designed in this paper adopts an internal compensation structure, which has good stability, simple design, small main chip area, simple peripheral equipment, and good application value. [ABSTRACT FROM AUTHOR]

Due to the rapid development of consumer electronics, the demand for power adapters is increasing. Therefore, a high-precision, high-reliability, low-cost flyback AC–DC converter without auxiliary winding was proposed in this paper. The converter adopted a primary-side regulation (PSR) topology to sample the output voltage and current from the primary inductor, and adjusted the switching frequency to achieve a constant output voltage. By alternately switching the main power BJT and the auxiliary MOSFET, with the advantage of the base charge storage effect, the chip was powered by the primary-side current. A primary-side sampling resistor was placed at the negative terminal of the ground potential of the chip, which approached real-time monitoring of the primary-side current. This improved the reliability and output accuracy of the system. To verify the feasibility and performance of the proposed circuit, an IC controller was designed and fabricated under the NEC 1 μm BCD process. Experimental result showed that deviations of the output voltage and current do not exceed ± 1.4% and ± 2.3%, respectively. These results also showed that the maximum conversion efficiency can reach a level of 78.7%, which satisfies the consumer market very well. [ABSTRACT FROM AUTHOR]

In this paper, a quasi-resonant (QR) flyback primary-side regulation (PSR) converter with adaptive frequency control is proposed. The converter adopts the PSR scheme to detect load information through the auxiliary winding. The converter employs the QR control scheme to switch in the valley mode either in CV or CC operation, which greatly reduces the switching loss. In addition, according to the load condition, the converter adaptively reduces the switching frequency and realize valley switching, which achieves better light-load efficiency in the CV mode. The proposed QR converter was implemented using the HHGRACE 0.35 μm BCD process and verified in a 5 V/1A circuit prototype. Experimental results show that the light-load power efficiency of the proposed converter is improved by up to 4.0% when compared to the conventional QR controller. In addition, the valley switching is realized under different load conditions, which improves the system efficiency in the entire range of output load. [ABSTRACT FROM AUTHOR]

This paper presents electrolytic capacitorless AC/DC LED driver. It adopts Boost–Buck topology, through modulation of the conduction time T on and the change of input current reference, to reduce the instantaneous input and output power difference, so a smaller film capacitor can be used instead of the electrolytic capacitor. Therefore, LED driver power life has been effectively improved. The Buck converter operates in the inductor current discontinuous conduction mode to achieve constant output current by controlling the peak current. The control IC is fabricated in TSMC 0.35- μ m 5-V/650-V CMOS/LDMOS process, and verified in a 72-V/150-mA circuit prototype. The test results show that when the range of input voltage is 175–264 Vac, the efficiency of the system is 83%, the voltage linear regulation is ± 1 %, the load regulation is ± 0. 5 %, and the electrolytic capacitor is replaced by 470-nF CBB capacitor under the condition that the power factor is above 0.7. Therefore, the design of the control chip in the LED driver has a very good application prospect. [ABSTRACT FROM AUTHOR]

With the development of portable electronic products, the requirement for chargers is also getting higher. In this paper, a high-accuracy constant output current/constant output voltage (CC/CV) ac–dc flyback converter is proposed and a novel cable compensation method without external capacitor is put forward. The converter adopts primary-side regulation (PSR) scheme, detecting the output voltage through the auxiliary winding, and adjusting switching frequency to achieve output voltage constant in CV mode. Compared to conventional cable compensation module, the proposed circuit applies a method of pre-filtering, averaging, and re-filtering, to obtain the compensation voltage. This method eliminates the need of external capacitor, reducing cost and increasing reliability of the converter. In CC mode, the switching period is adjusted to be fixed multiple of the demagnetization time, thereby realizing the constant current output. The control chip was implemented in NEC 1 μm HVCMOS process, and a 5-V/1-A prototype has been built to verify its feasibility. Experimental results show that the deviations of output voltage and current are within ±0.9% and ±3% under different inputs and loads, while maximum conversion efficiency can reach a level of 78.2%. [ABSTRACT FROM AUTHOR]

In this paper, based on the combination scheme of dual-sampling and adaptive predictive PID control, a digital controller for improving the transient performance of Buck DC–DC converters is designed. Due to the inherent loop delay in analog-to-digital (A/D) conversion, the calculation process of the digital controller and digital pulse width modulator (DPWM) of conventional digitally-controlled Buck DC–DC converters limits the system bandwidth and this makes the transient response lower. The designed digital controller can reduce the delay time in analog-to-digital converter (ADC), the digital controller and DPWM of digitally-controlled Buck DC–DC converters. Adaptive predictive control is used to eliminate the delay time of ADC and the digital controller, while dual-sampling scheme is used to reduce the delay time of DPWM in this paper. These are two new control schemes, and they show better performance in improving the transient response than other existing control schemes. Both simulation and experimental results demonstrate that the designed digital controller based on dual-sampling and adaptive predictive PID control is effective in improving the transient performance of Buck DC–DC converters. During experimental verification, for a load step between 0.5 A and 1.0 A, the fastest transient recovery time and the overshoot voltage are found to be 102 μ s and 120 mV, respectively. Compared with the conventional digital PID controller, the transient recovery time and the overshoot voltage of the digital controller designed in this paper are decreased by 40.0% and 27.3%, respectively. [ABSTRACT FROM AUTHOR]

A constant voltage AC-DC converter based on the digital assistant technology is proposed in this paper, which has the advantage of high output precision. In this paper, a novel digital exponential wave generator is adopted in Constant Voltage (CV) mode to replace the normal triangle waveform to obtain a wider range of switching frequency, increasing the accuracy of output voltage under light load. The control chip is implemented based on NEC 1m 5V/40V HVCMOS process, and a 5V/1.2A prototype has been built to verify the proposed control method. In PFM mode the deviation of output voltage is within % and the load regulation is %. Meanwhile, when the load jumps from light to heavy, the minimum output voltage could be maintained above 4.16V. [ABSTRACT FROM AUTHOR]

A flyback converter based on the two-stage exponential compensation is presented to reduce the system standby power consumption in this paper. The first-stage exponent circuit is achieved by RC integral circuit, and the waveform has a large slope at the beginning and it can close the power switch fast. The second stage exponent circuit is used to slow the rising trend of the exponent, especially before switching point, and makes the exponent circuit stop working after switching point. A proposed control IC has been fabricated in TSMC0.35 µm 5 V/600 V CMOS/LDMOS process. The experimental results indicate that the constant output voltage is 5 V, its precision is within ±4% and the standby power consumption is reduced by 30% in a wide range of universal input ac voltage from 90 V to 260 V, the average efficiency of the system is 89%, the system standby power is only 22 mW at 90 V input voltage, which meets the standby power requirements of the latest energy star on the AC/DC converter. [ABSTRACT FROM AUTHOR]

This paper proposes a high-precision primary-side regulation constant voltage (CV) and constant current (CC) ac–dc converter. CV output is achieved by adjusting the switching frequency and primary peak voltage simultaneously, for better dynamic adjustment ability. In order to improve CV precision, a cable compensation module is adopted to inject current to pull-down resistor of auxiliary winding divider, compensating the cable voltage loss caused by the output cable resistance. On the other hand, CC output is acquired by maintaining the ratio of switching frequency and output voltage constant. The inductance compensation module regulates further to keep the product of demagnetization time and switching frequency fixed, equalizing the inconsistent output current result from the big tolerance of the transformer primary-side inductance in the same batch. Moreover, an improved demagnetization time detector is proposed, which is beneficial to raise CC precision. The control chip is implemented based on TSMC 0.35-μm 5-V/40-V BCD process, and a 12 V/1 A prototype has been built to prove the proposed control method. In CV mode, the deviation of the output voltage is within ±1.5%, while that of output current is within ±3% in CC mode. [ABSTRACT FROM AUTHOR]

A novel digital constant output current controller with demagnetization-time compensation for flyback converter is proposed in this paper. The secondary winding demagnetization time is sampled from the comparison module output signal by output voltage sampling state machine. The ratio between and switching period is kept constant by bidirectional counter module to achieve constant output current based on invariable primary-side peak-current. Meanwhile, demagnetization-time compensation is proposed in order to enhance load regulation ratio. The compensation acquired from a look-up table, is utilized to compensate the impacts caused by the delay from the process of sampling the signal of . The digital controller (DC) is implemented by hardware description language Verilog HDL. Experimental results of the proposed 2A constant current output flyback converter based on FPGA(EP2C8Q208C8N) indicate that the constant current precision is within 1% in a wide range of universal-input AC voltage from 110V to 240V and the voltage load range between 2V and 8V. [ABSTRACT FROM AUTHOR]

In order to achieve high efficiency in a wider load range, a PWM/PFM/Power-Saved mode dc–dc buck converter is proposed. The mode switching technique is based on an accurate power loss model consisting of critical components/parameters: The size of the power transistor and the ON/OFF status of power-hungry subcircuits. The circuit of mode switching technique is achieved by the reference, pulse skipped modulation (PSM) comparator and feedback resistors, and its own consumption of quiescent current is extremely low. At ultra-light load, by detecting the ZCD duration and the ripple of the output, the system can switch to the Power-Saved-Mode. The proposed buck converter was implemented by using a 0.18 μ m CMOS process. It achieves a peak efficiency of 97% and > 90% efficiency from 100 μ A to 600 mA. A 360 nA quiescent current is achieved. With a low output ripple of less than 60 mV, the input voltage range and regulated output voltage are 3.6–5 V and 1.2–3.3 V, respectively. [ABSTRACT FROM AUTHOR]

With the development of electric vehicles, the demand for the high-voltage low-current DC-DC chips used in vehicle on-board equipment continues to grow. To improve the efficiency of the switching power supply, an asynchronous buck high-voltage DC-DC converter with adaptive variable frequency modulation (AVFM) technology is designed in this paper. This work focuses on the efficiency optimization of the buck converter, and the relationship between power consumption and operating frequency under different loads. The optimal frequency range is selected during light and heavy loads, and adaptive transition of the frequency is realized during a medium load. Using a threshold voltage (Vth_cs) circuit with an adjustable current inside the chip, the on-time of the switch is changed to realize frequency conversion. The whole chip design is based on 0.35 μm BCD process, in which the integrated LDMOS can withstand 200 V. System simulations are completed in Cadence. The results show that when the input voltage is 30–60 V and the output specification is 5 V/0.5 A, the system realizes adaptive frequency conversion in the entire load range, and the efficiency reaches 88.9%. The actual performance of the chip meets the design requirements and has good EMI characteristics. [ABSTRACT FROM AUTHOR]

In this paper, an adaptive multi-mode PWM control PSR flyback converter is proposed. In constant voltage (CV) mode, the converter adopts primary-side regulate (PSR) scheme to detect load information through the auxiliary winding, which reflects the load information on the voltage of V C O M P . The converter adjusts the switching frequency according to the voltage of V C O M P under different load conditions, realizing adaptive multi-mode PWM control to significantly improve light- load efficiency and thus the overall average efficiency. Besides, it does not give compromise to other system performance, such as audible noise, standby power consumption, and regulation. To verify the feasibility and performance of the proposed circuit, the converter has been designed and fabricated in HHGRACE_0.35 μ m BCD process and verified in a 5V/1A circuit prototype. The experimental results show that 25% load power efficiency of the proposed converter is 78.1%, which is improved by up to 3.4% compared to the conventional converter. [ABSTRACT FROM AUTHOR]

A primary-side regulation (PSR) constant current (CC) output and constant voltage (CV) output AC–DC converter is proposed and an adaptive high-precision closed-loop constant current control scheme is put forward in this paper. In the CC mode, the converter adopts the closed-loop control strategy to realize that the switching period adaptively converges to twice the demagnetization time, which realizes the CC output. In addition, exactly detecting the demagnetization time is a prerequisite for obtaining a high-precision output current. Therefore, a demagnetization time detection circuit is designed to provide accurate and reliable demagnetization information. The control IC was fabricated with the Nuvoton 0.5um BCD process, and a 5 V/2 A prototype circuit was implemented to verify its performance. Experimental results show that the CC deviation is within ± 1.4%, which is lower than the target value of ± 2.0%. Under different loads and AC inputs, the conversion efficiency in the CC mode varies between 76.3% and 80.7%. [ABSTRACT FROM AUTHOR]

To balance the output stability and maximum efficiency of a system, an efficiency optimization method based on adaptive frequency control is proposed. In this paper, load transmission is carried out using a DC–DC converter at the receiving end. When the load changes, controlling the rectified output voltage is carried out to realize the maximum efficiency point tracking. Meanwhile, the duty cycle of the rear stage DC–DC converter is changed to keep the output voltage constant. The sampled rectified voltage is compared with the estimated value and the resulting error data are sent to the system transmitter through ASK modulation wireless communication. Then the transmitter demodulation communication information through PID algorithm control is used to achieve the frequency of the adaptive adjustment. The feasibility of the proposed method has been verified by the simulation and experimental results. When the output voltage is 5 V, the constant voltage accuracy is within ± 1%, the maximum efficiency is up to 79.2%, and the dynamic response time is only 160 ms. [ABSTRACT FROM AUTHOR]