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276 results on '"Chandel, Rajeevan"'

8. Energy Efficient SRAM Design Using FinFETs and Potential Alteration Topology Schemes

Author

Agarwal, Samarth, Chandel, Rajeevan, Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Li, Yong, Series Editor, Liang, Qilian, Series Editor, Martín, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zamboni, Walter, Series Editor, Zhang, Junjie James, Series Editor, Mishra, Biswajit, editor, Mathew, Jimson, editor, and Patra, Priyadarsan, editor

Published
2022
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14. Fixed-Point Divider Using Newton Raphson Division Algorithm

Author

Pandey, Pawan Kumar, Singh, Dilip, Chandel, Rajeevan, Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Li, Yong, Series Editor, Liang, Qilian, Series Editor, Martín, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zhang, Junjie James, Series Editor, Nath, Vijay, editor, and Mandal, J. K., editor

Published
2021
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15. An Efficient FPGA-Based Accelerator for Perceptual Weighting Filter in Speech Coding.

Author

Singh, Dilip and Chandel, Rajeevan

Subjects
*SPEECH processing systems, *VIDEO coding, *AUTOMATIC speech recognition, *SIGNAL denoising, *MOVING average process, *MATHEMATICAL optimization, *COMPUTATIONAL complexity, *GRAPES
Abstract

In speech coding, denoising of the speech signal is essential as well as crucial. The filters for minimizing errors through denoising employ the autoregressive moving average (ARMA) approach, introducing higher computational complexity in speech coder design. This research work presents the design and implementation of an effective perceptual weighting filter (PWF) for speech coding. The high-level synthesis of the fixed-point PWF filter is optimized by multiple optimization techniques along with detailed design space exploration using the weighted sum (WS) method. To enhance the performance, an FPGA-based hardware accelerator is proposed using hardware/software (HW/SW) co-design in an embedded environment. Simulative analysis in Vivado HLS and final accelerator design in the Vitis IDE tool validate the proposed architecture by using real-time speech samples, demonstrating a 50% reduction in area and a 99% execution improvement. This makes it well-suited for use in modern speech codecs, enhancing the efficiency. [ABSTRACT FROM AUTHOR]

Published
2024
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21. Carbon Nanotube Based Delay Model For High Speed Energy Efficient on Chip Data Transmission Using: Current Mode Technique

Author

Jadav, Sunil, Vashistah, Munish, and Chandel, Rajeevan

Subjects
Computer Science - Emerging Technologies
Abstract

Speed is a major concern for high density VLSI networks. In this paper the closed form delay model for current mode signalling in VLSI interconnects has been proposed with resistive load termination. RLC interconnect line is modelled using characteristic impedance of transmission line and inductive effect. The inductive effect is dominant at lower technology node is modelled into an equivalent resistance. In this model first order transfer function is designed using finite difference equation, and by applying the boundary conditions at the source and load termination. It has been observed that the dominant pole determines system response and delay in the proposed model. Using CNIA tool (carbon nanotube interconnect analyzer) the interconnect line parameters has been estimated at 45nm technology node. The novel proposed current mode model superiority has been validated for CNT type of material. It superiority factor remains to 66.66% as compared to voltage mode signalling. And current mode dissipates 0.015pJ energy where as VM consume 0.045pJ for a single bit transmission across the interconnect over CNT material. Secondly the damping factor of a lumped RLC circuit is shown to be a useful figure of merit., Comment: 12 Figures, appears in Electrical and Electronics Engineering: An International Journal, November 2014

Published
2014
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22. Analysis of IR Drop for Robust Power Grid of Semiconductor Chip Design: A Review

Author

Fatima Bushra and Chandel Rajeevan

Subjects
Information technology, T58.5-58.64
Abstract

Modern semiconductor industry has a major focus on die size reduction and favours the usage of multiple metal layers to increase gross margins. High congestion and voltage or IR drop challenges result from designs with higher and lower core utilisations. Owing to this issue, one of the major difficulties in large silicon-on-chip (SoC) design is the implementation of a power grid design. It’s essential to correctly analyze IR drops to guarantee the reliability of the power grid. This paper presents a comprehensive review approach for the analysis of IR drop for robust power grid design in semiconductor chips. The necessity of the vector-based dynamic analysis and the drawbacks of the vector-less analysis have been addressed. The various techniques used to mitigate IR drop effects, including power grid modeling techniques, use of decoupling capacitors, and voltage drop analysis are explored. The review concludes by identifying the most promising techniques for robust power grid design in semiconductor chips and providing recommendations for future research. The simulations are carried out using ANSYS RedHawk, and the analysis findings are achieved using FinFET technology.

Published
2023
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23. Performance Analysis of Current-Mode Interconnect System in Presence of Process, Voltage, and Temperature Variations

Author

Agrawal, Yash, Parekh, Rutu, Chandel, Rajeevan, Angrisani, Leopoldo, Series editor, Arteaga, Marco, Series editor, Chakraborty, Samarjit, Series editor, Chen, Jiming, Series editor, Chen, Tan Kay, Series editor, Dillmann, Ruediger, Series editor, Duan, Haibin, Series editor, Ferrari, Gianluigi, Series editor, Ferre, Manuel, Series editor, Hirche, Sandra, Series editor, Jabbari, Faryar, Series editor, Kacprzyk, Janusz, Series editor, Khamis, Alaa, Series editor, Kroeger, Torsten, Series editor, Ming, Tan Cher, Series editor, Minker, Wolfgang, Series editor, Misra, Pradeep, Series editor, Möller, Sebastian, Series editor, Mukhopadhyay, Subhas Chandra, Series editor, Ning, Cun-Zheng, Series editor, Nishida, Toyoaki, Series editor, Panigrahi, Bijaya Ketan, Series editor, Pascucci, Federica, Series editor, Samad, Tariq, Series editor, Seng, Gan Woon, Series editor, Veiga, Germano, Series editor, Wu, Haitao, Series editor, Zhang, Junjie James, Series editor, Garg, Amik, editor, Bhoi, Akash Kumar, editor, Sanjeevikumar, Padmanaban, editor, and Kamani, K. K., editor

Published
2018
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24. Electrical characterization and performance analysis of coaxial through-glass vias.

Author

Boora, Vandana, Kumar, Ajay, Kommukuri, Madhukiran, Chandel, Rajeevan, and Dhiman, Rohit

Subjects
MULTIWALLED carbon nanotubes, FILLER materials, INSERTION loss (Telecommunication), COPPER, CIRCUIT elements, SUBSTRATE integrated waveguides
Abstract

In this paper, we have proposed the precise model of coaxial TGVs (CTGVs) which consists of ground-signal signal-ground (GSSG) TGVs. An equivalent electrical model of CTGVs is established and the partial element equivalent circuit (PEEC) technique is used to extract the frequency-dependent impedance parameters. In CTGVs, multi-walled carbon nanotubes (MWCNT) and copper is used as filler material in inner and outer layer. Resistance and inductance of CTGVs is calculated using the PEEC technique for different filler materials. The insertion loss (S21) of CTGVs is determined using the HFSS simulations and is compared analytically in differential mode configurations. S21 is calculated for various geometrical parameters of MWCNT-based CTGVs such as diameter of TGV, pitch between CTGV pair, as well as material properties such as permittivity of SiO2 and benzocyclobutene (BCB) polymers. It is established that MWCNT based CTGV shows improved insertion loss because the conductivity of MWCNT is higher in comparison to copper. [ABSTRACT FROM AUTHOR]

Published
2024
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25. Design and Analysis of a High-Performance N-Bit Digital Comparator Using a Novel EX-OR-NOR Gate.

Author

FATIMA, BUSHRA, CHANDEL, RAJEEVAN, and DHIMAN, ROHIT

Subjects
COMPARATOR circuits, ELECTRONIC design automation, DIGITAL electronics, HYBRID integrated circuits, SUCCESSIVE approximation analog-to-digital converters, ELECTRONIC systems, BIT error rate
Abstract

This paper presents the design and analysis of high-performance N-bit digital comparators for use in modern digital systems. Digital comparators are fundamental building blocks in many electronic systems, performing the critical task of comparing two digital values and generating an output indicating their relative magnitudes. For implementing N-bit digital comparator a new design for an 8T EX-OR-NOR cell with full rail-to-rail output swing has been proposed. The proposed EX-OR-NOR cell is based on the hybrid circuit utilizing CMOS inverter and transmission gate logics, which thereby uses less power and minimizes propagation delay. Thus, a high-speed N-bit digital comparator design is accomplished using the proposed 8T EX-OR-NOR cell. In the present work 4-bit to 32-bit digital comparators are designed and implemented using the proposed circuitry. All the circuits are designed using Cadence electronic design automation (EDA) Virtuoso Design Environment for 180nm CMOS technology node. The outcomes are evaluated and verified with the comparator designs reported in the literature. The proposed modified N-bit digital comparators provide an excellent combination of speed, power consumption, and accuracy, making them a promising solution for modern digital electronics systems. [ABSTRACT FROM AUTHOR]

Published
2024

27. Stability Analysis of Carbon Nanotube Interconnects

Author

Kumar, Mekala Girish, Agrawal, Yash, Chandel, Rajeevan, Kacprzyk, Janusz, Series editor, Pal, Nikhil R., Advisory editor, Bello Perez, Rafael, Advisory editor, Corchado, Emilio S., Advisory editor, Hagras, Hani, Advisory editor, Kóczy, László T., Advisory editor, Kreinovich, Vladik, Advisory editor, Lin, Chin-Teng, Advisory editor, Lu, Jie, Advisory editor, Melin, Patricia, Advisory editor, Nedjah, Nadia, Advisory editor, Nguyen, Ngoc Thanh, Advisory editor, Wang, Jun, Advisory editor, Deiva Sundari, P., editor, Dash, Subhransu Sekhar, editor, Das, Swagatam, editor, and Panigrahi, Bijaya Ketan, editor

Published
2017
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28. Time-Domain Analytical Modeling of Current-Mode Signaling Bundled Single-Wall Carbon Nanotube Interconnects

Author

Agrawal, Yash, Girish, M., Chandel, Rajeevan, Kacprzyk, Janusz, Series editor, Pal, Nikhil R., Advisory editor, Bello Perez, Rafael, Advisory editor, Corchado, Emilio S., Advisory editor, Hagras, Hani, Advisory editor, Kóczy, László T., Advisory editor, Kreinovich, Vladik, Advisory editor, Lin, Chin-Teng, Advisory editor, Lu, Jie, Advisory editor, Melin, Patricia, Advisory editor, Nedjah, Nadia, Advisory editor, Nguyen, Ngoc Thanh, Advisory editor, Wang, Jun, Advisory editor, Deiva Sundari, P., editor, Dash, Subhransu Sekhar, editor, Das, Swagatam, editor, and Panigrahi, Bijaya Ketan, editor

Published
2017
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32. Introduction

Author

Dhiman, Rohit, Chandel, Rajeevan, Rashid, Muhammad H, Series editor, Dhiman, Rohit, and Chandel, Rajeevan

Published
2015
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50. A Proposal, Design, and Analysis of Planar Feed Gasket Antennas with Modified Substrate for Multiband Vehicular Applications.

Author

Kaushal, Deepanshu and Chandel, Rajeevan

Subjects
*ANTENNA feeds, *MONOPOLE antennas, *ANTENNAS (Electronics), *ANTENNA design, *GASKETS
Abstract

The Sierpinski Gasket fractal antennas can provide the best generic multiband behaviour among the several planar feed monopole antennas available for use in automotive applications. The Gasket geometries used in antennas can be classical, scale perturbed, or both scale and flare perturbed. When used in the planar feed configuration, the classical and perturbed Gasket fractal antennas suffer from considerable reflections at one or more multiband frequencies, rendering these frequencies unsuitable for usage. Therefore, a design modification in these antennas is essential. A novel design modification has been proposed in the Sierpinski Gasket fractal antennas in the present research work by utilizing metamaterial engineered substrates. It has been found that the metamaterials not only reduce reflections but these materials also lower Gasket antenna frequencies, thereby, facilitating reduction in the antenna size. The findings have been validated through the experimental investigations. The comprehensive design analysis presented in the present paper shall prove highly beneficial to the antenna designers in rapidly customizing the vehicular antennas. [ABSTRACT FROM AUTHOR]

Published
2023
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