101 results on '"Chakradhar, S.T."'
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2. Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques
3. Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC
4. Cypress: compression and encryption of data and code for embedded multimedia systems
5. A parallel accelerator for semantic search.
6. Scalable effort hardware design: Exploiting algorithmic resilience for energy efficiency.
7. A framework for efficient and scalable execution of domain-specific templates on GPUs.
8. Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor.
9. A low cost test data compression technique for high n-detection fault coverage.
10. A High Compression and Short Test Sequence Test Compression Technique to Enhance Compressions of LFSR Reseeding.
11. Power monitors: a framework for system-level power estimation using heterogeneous power models.
12. Distance restricted scan chain reordering to enhance delay fault coverage.
13. Heterogeneous and multi-level compression techniques for test volume reduction in systems-on-chip.
14. Response shaper: a novel technique to enhance unknown tolerance for output response compaction.
15. ChiYun compact: a novel test compaction technique for responses with unknown values.
16. Re-configurable embedded core test protocol.
17. A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs.
18. Accurate power macro-modeling techniques for complex RTL circuits.
19. Resynthesis and retiming for optimum partial scan
20. Bottleneck removal algorithm for dynamic compaction in sequential circuits
21. Redundancy removal and test generation for circuits with non-Boolean primitives
22. Synthesis of initializable asynchronous circuits
23. Energy models for delay testing
24. Combinational ATPG theorems for identifying untestable faults in sequential circuits
25. Test function embedding algorithms with application to interconnected finite state machines
26. A partition and resynthesis approach to testable design of large circuits
27. First-order versus second-order single-layer recurrent neural networks
28. Testing high speed VLSI devices using slower testers.
29. A transitive closure algorithm for test generation
30. Performance analysis of synchronized iterative algorithms on multiprocessor systems
31. Initialization issues in the synthesis of asynchronous circuits.
32. Redundancy removal and test generation for circuits with non-Boolean primitives.
33. Software transformations for sequential test generation.
34. Partial scan design for technology mapped circuits.
35. Optimum retiming of large sequential circuits.
36. A novel VLSI solution to a difficult graph problem.
37. Logic simulation and parallel processing.
38. Polynomial time solvable fault detection problems.
39. Automatic test generation using neural networks.
40. Test function embedding algorithms with application to interconnected finite state machines.
41. Retiming with logic duplication transformation: theory and an application to partial scan.
42. Synchronous test generation model for asynchronous circuits.
43. Dynamic test sequence compaction for sequential circuits.
44. Sequential circuits with combinational test generation complexity.
45. Synthesis of initializable asynchronous circuits.
46. A test function architecture for interconnected finite state machines.
47. Retiming sequential circuits to enhance testability.
48. Discrete test generation by continuous methods.
49. A synthesis approach to design for testability.
50. A synthesis for testability technique for PLA-based finite state machines.
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