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Gallium oxide (β-Ga2O3) is becoming a popular material for high power electronic devices due to its wide bandgap and ease of processing. In this work, β-Ga2O3 substrates received various annealing treatments before atomic layer deposition of HfO2 and subsequent fabrication of metal–oxide–semiconductor (MOS) capacitors. Annealing of β-Ga2O3 with forming gas or nitrogen produced degraded capacitance–voltage (C–V) behavior compared to a β-Ga2O3 control sample with no annealing. A sample annealed with pure oxygen had improved C–V characteristics relative to the control sample, with a higher maximum capacitance and smaller flat-band voltage shift, indicating that oxygen annealing improved the C–V behavior. X-ray photoelectron spectroscopy also suggested a reduction in the oxygen vacancy concentration after O2 annealing at 450 °C, which supports the improved C–V characteristics and indicates that O2 annealing of β-Ga2O3 may lead to better MOS device performance.

Performance and reliability comparison of oxide-based thin-film transistors fabricated at a maximum process temperature of 115 °C is presented. A fully patterned and passivated process was successfully evaluated and implemented using polycrystalline ZnO and amorphous indium–gallium–zinc–oxide (IGZO) as an active layer in glass substrates. Saturation mobilities of 14.2 and 9.0 cm $^{{2}}\cdot \text{V}^{-{1}}\cdot \text{s}^{-{1}}$ were obtained for ZnO and IGZO, respectively, with threshold voltages of 2.2 and 2.0 V, an ON/ OFF ratio $> {1} \times 10^{{8}}$ , and an ${I}_{{\text {off}}} A. The small mobility change in IGZO with gate voltage is due to its amorphous character. Longer variation is observed in polycrystalline ZnO due to its grain boundaries. Reliability studies show a threshold voltage shifting of 0.4 and 1.8 V for ZnO and IGZO devices, testing after 1200-s stress. Devices were successfully implemented in ZnO- and IGZO-based inverters using saturation and zero-drive structures, showing a maximum dc gain of 2.4- and 25-V/V, respectively.

As β-Ga2O3 becomes a popular semiconductor material for high-power electronic devices, researchers are presenting innovative device structures and fabrication processes to achieve high performance and enhanced reliability of these devices. In many cases, these fabrication processes involve the formation of mesas, trenches, and other structures by plasma etching of β-Ga2O3 with Cl2 and/or BCl3. This paper looks at the effects of photoresist patterning and BCl3 plasma etching prior to atomic layer deposition of HfO2 dielectric to form metal–oxide–semiconductor capacitors. The β-Ga2O3/HfO2 interface is critical for controlling device characteristics such as flat-band voltage and maximum capacitance under accumulation and can be greatly affected by roughness and chemical residues. Capacitance-voltage data and atomic force microscope (AFM) scans indicate that photoresist and BCl3 residues are not adequately removed with acetone/IPA/DIW cleaning but are removed using piranha (H2O2/H2SO4) cleaning before deposition of the dielectric.

In this study, we report the recoverable energy density (Urec) of lead-free antiferroelectric perovskite 0.92(Bi0.54Na0.46)TiO3-0.08BaTiO3 (BNT-BT) ultrathin films deposited directly on highly boron-doped silicon (p-Si) by a pulsed laser deposition method. Two pressure values were used in the growing conditions, 4.67 × 10−5 and 13.3 Pa, at a fixed substrate temperature of 700 °C. After that, the films were subjected to postannealing under an oxidizing atmosphere at 700 °C for 1 h. A conventional lithography process was used to define vertical metal–ferroelectric–p-Si structures and evaluate the energy storage characteristics. Cross-sectional SEM images showed achieved thicknesses of about 11–13 nm. The high electric field strengths of 3.8 and 4.5 MV/cm supported for BNT-BT ultrathin films deposited at 4.67 × 10−5 and 13.3 Pa, respectively, imply a high-quality perovskite thin-film growth on p-Si. The 11-nm ultrathin film grown at 13.3 Pa showed higher Urec, efficiency (η), and a maximum applied electric field of 30 J/cm3, 83%, and 4.5 MV/cm, respectively.

The discovery of ferroelectricity in HfO2-based materials in 2011 provided new research directions and opportunities. In particular, for atomic layer deposited Hf0.5Zr0.5O2 (HZO) films, it is possible to obtain homogenous thin films with satisfactory ferroelectric properties at a low thermal budget process. Based on experiment demonstrations over the past 10 years, it is well known that HZO films show excellent ferroelectricity when sandwiched between TiN top and bottom electrodes. This work reports a comprehensive study on the effect of TiN top and bottom electrodes on the ferroelectric properties of HZO thin films (10 nm). Investigations showed that during HZO crystallization, the TiN bottom electrode promoted ferroelectric phase formation (by oxygen scavenging) and the TiN top electrode inhibited non-ferroelectric phase formation (by stress-induced crystallization). In addition, it was confirmed that the TiN top and bottom electrodes acted as a barrier layer to hydrogen diffusion into the HZO thin film during annealing in a hydrogen-containing atmosphere. These features make the TiN electrodes a useful strategy for improving and preserving the ferroelectric properties of HZO thin films for next-generation memory applications.

The discovery of ferroelectricity in HfO2-based materials in 2011 provided new research directions and opportunities. In particular, for atomic layer deposited Hf0.5Zr0.5O2 (HZO) films, it is possible to obtain homogenous thin films with satisfactory ferroelectric properties at a low thermal budget process. Based on experiment demonstrations over the past 10 years, it is well known that HZO films show excellent ferroelectricity when sandwiched between TiN top and bottom electrodes. This work reports a comprehensive study on the effect of TiN top and bottom electrodes on the ferroelectric properties of HZO thin films (10 nm). Investigations showed that during HZO crystallization, the TiN bottom electrode promoted ferroelectric phase formation (by oxygen scavenging) and the TiN top electrode inhibited non-ferroelectric phase formation (by stress-induced crystallization). In addition, it was confirmed that the TiN top and bottom electrodes acted as a barrier layer to hydrogen diffusion into the HZO thin film during annealing in a hydrogen-containing atmosphere. These features make the TiN electrodes a useful strategy for improving and preserving the ferroelectric properties of HZO thin films for next-generation memory applications.

Positive bias instability stress (PBI) and hot carrier injection stress (HCI) was done on ZnO thin-film transistors (TFTs) with 100°C Al 2 O 3 . The threshold voltage (V T ), transconductance (g m ), and subthreshold slope (SS) were monitored. HCI stress with two intermittent sense measurements where the first I DS -V GS is measured at the drain contact and the second is measured at the source contact to separate the contribution of the hot carrier and cold carrier injection on the V T shift. PBI stress was done to determine the viability of the carrier injection separation using only HCI.

Increasing interest in the development of alternative energy storage technologies has led to efforts being taken to improve the energy density of dielectric capacitors with high power density. However, dielectric polymer materials still have low energy densities because of their low dielectric constant, whereas Pb-based materials are limited by environmental issues and regulations. Here, the energy storage behaviors of atomic layer-deposited Hf1- XZr XO2 ( X = 0-1) thin films (10 nm) and the phase transformation mechanism associated with an enhancement of their energy density are reported using unipolar pulse measurements. Based on electrical and material characterization, the energy density and energy efficiency are dependent on the Zr content, and stress-induced crystallization by the encapsulating Hf1- XZr XO2 films with TiN top electrodes prior to annealing can enhance the energy density (up to 47 J/cm3 at a small voltage value of 3.5 MV/cm) while minimizing energy loss even at low process temperatures (400 °C). This work will facilitate the realization of Hf1- XZr XO2-based capacitors for lead-free electrostatic energy storage applications.

The role of specific atomic-scale defects involved in total ionizing dose radiation in the metal–oxide–semiconductor field-effect transistors of the 1980s and 1990s was identified in large part with electron paramagnetic resonance (EPR) techniques. The techniques involved in those studies were classical EPR and, to a lesser extent, electrically detected magnetic resonance (EDMR). We show that somewhat more sophisticated resonance-based measurements can be fruitfully applied to explore the atomic-scale basic mechanisms of the significantly more complex, generally messier, and much smaller devices of the present day. We present multifield and frequency EDMR measurements in which the response is observed via spin-dependent leakage currents, spin-dependent charge pumping, and spin-dependent gated diode recombination currents. We also exploit isotopic substitution, replacing hydrogen with deuterium, monitoring the isotopic effects on the resonance response. The approaches utilized in this paper should be applicable to radiation damage studies in a wide variety of emerging materials and devices.

We demonstrate that a new technique, near-zero field magnetoresistance (NZFMR) spectroscopy, can explore radiation damage in a wide variety of devices in a proof-of-concept study. The technique has great potential for the study of atomic-scale mechanisms of radiation damage in 3-D integrated circuits. In our study, we explore radiation damage in structures relevant to 3-D integrated circuits, but not on 3-D test structures themselves. Five structures of great technological importance to 3-D integrated circuits are investigated. We utilize both NZFMR and electrically detected magnetic resonance to investigate radiation effects in these structures. The structures involved in this paper are planar silicon metal–oxide–semiconductor field-effect transistors, silicon–germanium alloy-based transistors, fin-based transistors, silicon dioxide-based flowable oxides, and low-k dielectrics. Our study indicates that NZFMR has great potential in radiation damage studies, with exceptional promise in systems in which more conventional resonance is not possible.

The prolonged bias stress of ZnO TFTs transistors with Al 2 O 3 deposited at 100, 175, and 250°C is presented. Fully patterned bottom gated and top contacted devices serve as the test structures. The reliability study shows increasing threshold voltage shifting of 10.5, 18.6, and 27.2 % with deposition temperature with no significant change in the density of interface states for all the samples. Nevertheless, there is a dependence of the oxide trap states with stress time. The analysis of the transconductance as a function of the threshold voltage shifting indicates that oxide traps states near the interface are the dominant instability mechanism for significant stress times. The Al 2 O 3 deposited at a temperature of 100 °C contains a higher concentration of oxygen compared to the other samples. This present oxygen excess could be filling oxygen vacancies present in the Al 2 O 3 , thereby resulting in a smaller ΔV TH .

In this letter, we report gallium nitride-based metal-insulator-semiconductor high-electron-mobility transistors (GaN MIS-HEMTs) with a 16-nm-thick silicon nitride (SiN x ) gate insulator and surface passivation layer grown using low-temperature (300 °C) hollow cathode plasma-enhanced atomic layer deposition. Tris(dimethylamino) silane and a remote N2 plasma were used as the silicon precursor and the nitrogen co-reactant, respectively. Though the growth temperature was as low as 300 °C, we obtained excellent film properties such as a high refractive index (2.00), a high film density (2.9 g/cm3), and a low wet etch rate (0.8 nm/min) in 100:1 hydrofluoric acid. High-resolution transmission electron microscopy images of the gate stacks showed ~1.5 nm $\beta $ -phase Si3N4 crystalline interfacial layer on the GaN surface. The devices showed a negligible hysteresis of ~50 mV, a steep subthreshold slope of 76 mV/dec, and a high ON/OFF drain current ratio of ~109. In addition, the devices showed a small positive/negative bias temperature threshold voltage ( ${V}_{\text {th}}$ ) instability ( $\Delta {V}_{\text {th}}\le 0.2$ V at 25 °C and 150 °C) as well as a mitigated current collapse under an off-state quiescent ${V}_{\text {DS}}$ of 20 V.

Graphene, an allotrope of carbon, shows ambipolar transfer characteristics with a linear dispersion relation where the conduction and valence band meets at the Dirac point 1. Owing to an absence of bandgap, it is not feasible to use graphene in logic applications though it is possible to use graphene in analog and RF circuits2. Significant efforts towards the growth and transfer of graphene onto arbitrary substrates 3 4 , 5 6 has made it feasible to scale up graphene device fabrication – early focus on single, exfoliated devices has given way to large area, many-device wafers. From a practical standpoint, a lower operating voltage range, minimal unintentional doping of graphene during processing, and excellent device stability at room temperature is required. Most of the earlier graphene based devices were fabricated on thick (90nm or higher) thermal SiO2 substrate as they provide a better optical contrast after transferring graphene. Unfortunately, this attributes to a higher operating voltage in order to modulate the graphene device. In this work, we demonstrate the feasibility of making devices on thin, 10 nm thermal SiO­2 gate dielectric using CVD graphene with minimal shift in the Dirac point and excellent stability during subsequent operation cycles in air at room temperature. The 10nm thermal SiO2 has a breakdown field of ~9.7MV/cm and mobilities as high as 2200 cm2/V·S is achieved in a relatively small operating voltage (±8V). A higher mobility is typically seen for devices located at the center of the transferred graphene region. The 10nm dielectric used in our process is challenging for integration since graphene cannot be visually inspected during device fabrication, but we have overcome this limitation by implementing specialized characterization steps that allow us to monitor the graphene. A lower contact resistivity of 500 Ω-µm and sheet resistance (RSh) of 400Ω/□ is observed at a higher doping level achieved by applying a fixed back gate bias with Ni/Au contact. A similar trend is seen in the RSh extracted from a more appropriate test structure (Van der Pauw), wherein there is a minimal metal contact overlap with graphene. The hysteresis for these graphene devices are consistently less than or equal to 0.3V within the ± 8V sweeping voltage range. Therefore, we demonstrate the fabrication of wafer scale graphene devices with excellent process control on thin dielectric substrate with minimal doping and trapped charge. This could pave way for realization of high performance, low power consuming nanoelectronics with graphene. (1) Novoselov, K. S.; Geim, A. K.; Morozov, S. V.; Jiang, D.; Zhang, Y.; Dubonos, S. V.; Grigorieva, I. V.; Firsov, A. A. Electric Field Effect in Atomically Thin Carbon Films. Science. 2004, 306, 666–669. (2) Schwierz, F. Graphene Transistors. Nat. Nano. 2010, 5, 487–496. (3) Colombo, L.; Wallace, R. M.; Ruoff, R. S. Graphene Growth and Device Integration. Proc. IEEE 2013, 101, 1536–1556. (4) Banszerus, L.; Schmitz, M.; Engels, S.; Dauber, J.; Oellers, M.; Haupt, F.; Watanabe, K.; Taniguchi, T.; Beschoten, B.; Stampfer, C. Ultrahigh-Mobility Graphene Devices from Chemical Vapor Deposition on Reusable Copper. Sci. Adv. 2015, 1, e1500222(1-6). (5) Kim, H. H.; Lee, S. K.; Lee, S. G.; Lee, E.; Cho, K. Wetting-Assisted Crack- and Wrinkle-Free Transfer of Wafer-Scale Graphene onto Arbitrary Substrates over a Wide Range of Surface Energies. Adv. Funct. Mater. 2016,26, 2070-2077. (6) Li, X.; Cai, W.; An, J.; Kim, S.; Nah, J.; Yang, D.; Piner, R.; Velamakanni, A.; Jung, I.; Tutuc, E.; Banerjee,S. K;Colombo, L.; Ruoff. R. S . Large-Area Synthesis of High-Quality and Uniform Graphene Films on Copper Foils. Science . 2009, 324, 1312–1314.

This paper reports on the study of inverted metal-oxide semiconductor (MOS) structures formed through mechanical exfoliation of MoS2 flakes onto Al2O3 or SiO2 layers grown on degenerately doped p type silicon substrates. Using Au/Ni metal top contacts, multi-frequency capacitance and conductance characterisation were performed to investigate electrically active defects in the MoS2/oxide structures. This data has been paired with physics-based ac simulations which indicate close to ideal interfacial properties.

High quality HfO2 and Al2O3 substrates are fabricated in order to study their impact on top-gate MoS2 transistors. Compared with top-gate MoS2 FETs on a SiO2 substrate, the field effect mobility decreased for devices on HfO2 substrates but substantially increased for devices on Al2O3 substrates, possibly due to substrate surface roughness. A forming gas anneal is found to enhance device performance due to a reduction in charge trap density of the high-k substrates. The major improvements in device performance are ascribed to the forming gas anneal. Top-gate devices built upon Al2O3 substrates exhibit a near-ideal subthreshold swing (SS) of ~69mV/dec and a ~10 increase in field effect mobility, indicating a positive influence on top-gate device performance even without any backside bias. Display Omitted Top-gate MoS2 FETs were fabricated on high-k dielectric substrates.A forming gas anneal enhances device performance with a reduction in Dit.Top-gate devices on Al2O3/Si showed better performance than on HfO2/Si.AFM images suggest that substrate surface roughness affects device performance.

Recently, molybdenum disulfide (MoS

A test structure and measurement method are proposed that permits measurement of several resistors in parallel using a kelvin method with only two independent pads per device. This technique allows rapid measurement of several different resistors with efficient area usage and a simple and adaptable circuit architecture.

As novel semiconductor and dielectric materials become more prevalent in MOS device technology, MOS capacitors are used to investigate the quality of semiconductor/dielectric, semiconductor/contact, and dielectric/metal gate interfaces, through capacitance-voltage (C-V) and I-V testing along with physical materials characterization. Thermal processes such as implant stabilization, contact annealing, and dielectric postdeposition annealing must be managed to accomplish the desired results while minimizing undesirable side effects such as interdiffusion or dopant migration in devices. This can be done through a combination of device and process design, which prevents these unwanted effects through careful material selection, ordering of process steps, temperature adjustments where possible, and selection of process gases used during thermal treatments. This study focuses on the effects of a 430 °C forming gas anneal, which produced an unusual brown layer on Ti/Au metal-oxide-semiconductor capacitor gates. A series of experiments, XPS analysis, and C-V electrical data revealed that the brown layer was not an organic residue but a thin layer of TiO2 on the gold surface, which formed due to Ti diffusion to the Au surface during the forming gas anneal. Oxygen plasma treatment before the furnace anneal enhanced the undesirable diffusion effect. Replacing the Ti/Au gates with Cr/Au gates prevented the brown layer and improved capacitance-voltage characteristics.

Currently, transition metal dichalcogenides (TMDs) are under intense investigation due to their potential uses. [1] One reason for the interest is because TMDs exhibit a bandgap. This provides a key aspect that can enable their use in future transistors as alternative channel materials with high mobility values while also providing robust on/off ratios. Because of the need to overcome the short channel effects and lower the power consumption of field effect transistors (FETs) as their dimensions scaled down drastically, extensive research has been done on layer-by-layer TMDs over the past few years. [2-4] Furthermore, due to the variety of TMDs, which results in different bandgaps and overall offsets [5], there are theoretical predictions suggesting that TMDs are best introduced in “broken gap” tunneling field effect transistors (TFETs). Some of these device designs include dielectrics in contact with TMD material. As we wait for advances in TMD materials growth, researchers are investigating relevant TMDs with most transistor structures being bottom gate devices for the ease of integration with an emphasis on the TMD material. However, there have been very few studies to investigate high-k dielectrics on these TMD materials. [6-8] Furthermore, even fewer studies are done on the interface characterization between dielectric and TMD, with even fewer still on the evaluation of this interface electrically [9, 10] and the implications to device performance and reliability. An obstacle of integrating high-k dielectrics on these two-dimensional (2-D) materials is the lack of bonds available at the surface that enables thin film deposition. On the other hand, the research on metal/TMD contacts is also important to improve the transistor performance. To reduce the contact resistance, the metal selection [2], doping techniques [11] and the understanding of carrier transport near the metal/TMD interface [12] still require scientific investigation. Therefore, in this work, we will demonstrate top-gated few-layer MoS2 transistors with HfO2 dielectric and the subsequent electrical characterization. Few-layer MoS2 flakes were exfoliated from commercial natural MoS2 crystals and transferred onto the SiO2 /Si substrate. Using photolithography with a lift-off process, the source and drain of the transistor were formed with Au / Ti. Thereafter, a 15-minutes in-situ UV-O3 surface functionalization [6] was performed, and HfO2 was deposited at 200˚C using atomic layer deposition (ALD) immediately after the treatment. The final step of fabrication was deposition and patterning of Au / Cr metal gate. Electrical measurements were performed using a Keithley 4200 SCS and an Agilent E4980A LCR meter. The interface between MoS2 and HfO2 was studied by capacitance-voltage (C-V) measurements. Interface trap density (Dit) was extracted using the conventional high-low frequency method. From the characterization results of a MoS2 transistor, the IDS-VGS exhibited an Ion/Ioff ratio of 106, and an ultra-low leakage current (~10-14 A) indicating a continuous dielectric thin film. In C-V measurements, a “hump” was observed in the depletion region, which indicates a large number of interface traps in the gate stack. It explains the SS degradation in the I-V measurements. The IDS-VDS curves show a non-linear region at low VDS, which are caused by non-optimized contacts. Moreover, we extracted the Dit, where a peak value of 1.2×1013 cm-2eV-1 was extracted. More physical characterization and analysis are needed to understand the origin of these interface traps. With this transistor test structure; however, the ability to study other TMDs beyond MoS2, HfO2, and Au/Ti contacts are possible. This work is partially funded by National Science Foundation (NSF) award 1407765. References: [1] Q. H. Wang, et al., Nat. Nano., 7, p. 699, 2012. [2] S. Das, et al., Nano Letters, 13, p. 100, 2012. [3] H. Liu et al., IEEE EDL, 33, p. 546, 2012. [4] B. Radisavljevic, et al., Nat Nano, 6, p. 147, 2011. [5] C. Gong, et al., APL, 103, p. 053513, 2013. [6] A. Azcatl, et al., APL, 104, p. 111601, 2014. [7] S. McDonnell, et al., ACS Nano, 7, p. 10354, 2013. [8] J. Yang, et al., ACS Appl. Mat. & Int., 5, p. 4739, 2013. [9] W. Zhu, et al., Nat. Comm., 5, p. 3087, 2014. [10] P. Zhao, et al., Microelectron. Eng., 147, p. 151, 2015. [11] H. Fang, et al., Nano Lett., 13, p. 1991, 2013. [12] H. Liu, et al., ACS Nano, 8, p. 1031, 2014. Figure 1

In this paper pulsed laser deposition (PLD) methods are used to study p-n CdTe/CdS heterojunctions fabricated in-situ . In-situ film deposition allows higher quality p-n interfaces by minimizing spurious contamination from the atmosphere. Morphologic and structural analyses were carried for CdTe films deposited on various substrates and different deposition conditions. The electrical characteristics and performance of the resulting p-n heterojunctions were studied as function of substrate and post-deposition anneal temperature. In-situ growth results on diodes with a rectification factor of ~ 10 5 , an ideality factor − 8 A. The carrier concentration in the CdTe film was in the range of ~ 10 15 cm − 3 , as measured by C-V methods. The possible impact of sulfur diffusion from the CdS into the CdTe film is also investigated using High Resolution Rutherford Back-Scattering.

In this work, an example of practical implementation of the auxiliary sub-circuit (ASC) for modeling of the NBTI effects in DG FinFETs is described. A good agreement between the simulated and measured electrical characteristics of p-type DG FinFETs fabricated in SOI technology has been obtained using the industry-standard BSIM-CMG model with ASC. The oxide and interface trap densities are extracted in Spice simulations by tuning the ASC trapped charge parameters to fit the NBTI experimental data. The increase of oxide and interface trapped charge in p-type DG FinFET device is found to follow the logarithmic dependence with NBTI stress time.

Graphene field effect transistors (GFETs) are typically benchmarked based on their field effect mobility. Constant mobility model proposed by Kim1 et.al is extensively used to derive this mobility parameter by directly fitting the transfer curves of graphene devices. Various methodologies were suggested to supplant and improve this existing mobility model. Among them Zhang2 et.al suggested the need for using measured gate oxide capacitance in order to extract mobility for top-gated GFETs. One of the commonly overlooked features, in the case of back gated GEFTs is the dopant concentration or the resistivity of Si substrate used. Herein, we explore the dependence of graphene carrier mobility on the induced carrier concentration and depletion capacitance of underlying Si substrate. Si with resistivities 0.01-0.02 Ω-cm and 0.001-0.005 Ω-cm were used to grow 10 nm thermal SiO2. GFETs were fabricated using CVD graphene on top of this thermal oxide substrate and the corresponding transfer curves are co-related with the capacitance density measured from corresponding MOSCAP structure. Detailed carrier mobility extraction and results are presented. (1) Kim, S.; Nah, J.; Jo, I.; Shahrjerdi, D.; Colombo, L.; Yao, Z.; Tutuc, E.; Banerjee, S. K. Realization of a High Mobility Dual-Gated Graphene Field-Effect Transistor with Al2O3 Dielectric. Appl. Phys. Lett. 2009, 94 (6). https://doi.org/10.1063/1.3077021. (2) Zhang, Z.; Xu, H.; Zhong, H.; Peng, L. M. Direct Extraction of Carrier Mobility in Graphene Field-Effect Transistor Using Current-Voltage and Capacitance-Voltage Measurements. Appl. Phys. Lett. 2012, 101 (21). https://doi.org/10.1063/1.4768690.

Increasing interest in the development of alternative energy storage technologies has led to efforts being taken to improve the energy density of dielectric capacitors with high power density. However, dielectric polymer materials still have low energy densities because of their low dielectric constant, whereas Pb-based materials are limited by environmental issues and regulations. Here, the energy storage behaviors of atomic layer-deposited Hf

Top-gated, few-layer MoS2 transistors with HfO2 (6 nm)/Al2O3 (3 nm) gate dielectric stacks are fabricated and electrically characterized by capacitance–voltage (C–V) measurements to study electrically active traps (Dit) in the vicinity of the Al2O3/MoS2 interface. Devices with low Dit and high Dit are both observed in C–V characterization, and the impact of H2/N2 forming gas annealing at 300 and 400 °C on the Dit density and distribution is studied. A 300 °C anneal is able to reduce the Dit significantly, while the 400 °C anneal increases defects in the gate stack. Simulation with modeled defects suggests a sizable decrease in Dit, half the amount of positive fixed charge in the dielectric, and slightly increased unintentional doping in MoS2 after a 300 °C anneal. In the as-fabricated devices displaying high Dit levels, the energy distribution of the Dit located at the Al2O3/MoS2 interface is continuous from the conduction band edge of MoS2 down to 0.13–0.35 eV below the conduction band edge. A plausible Dit origin in our experiments could come from the unexpected oxygen atoms that fill the sulfur vacancies during the UV–O3 functionalization treatment. The border trap concentration in Al2O3 is the same, both before and after the anneal, suggesting a different origin of the border traps, possibly due to the low-temperature atomic-layer-deposited process.

Palladium has been widely employed as a hole contact to WSe2 and has enabled, at times, the highest WSe2 transistor performance. However, there are orders of magnitude variation across the literature in Pd–WSe2 contact resistance and ION/IOFF ratios with no true understanding of how to consistently achieve high-performance contacts. In this work, WSe2 transistors with impressive ION/IOFF ratios of 106 and Pd–WSe2 Schottky diodes with near-zero variability are demonstrated utilizing Ohmic-like Pd contacts through deliberate control of the interface chemistry. The increased concentration of a PdSex intermetallic is correlated with an Ohmic band alignment and concomitant defect passivation, which further reduces the contact resistance, variability, and barrier height inhomogeneity. The lowest contact resistance occurs when a 60 min post-metallization anneal at 400 °C in forming gas (FG) is performed. X-ray photoelectron spectroscopy indicates this FG anneal produces 3× the concentration of PdSex and an Ohmic band alignment, in contrast to that detected after annealing in ultrahigh vacuum, during which a 0.2 eV hole Schottky barrier forms. Raman spectroscopy and scanning transmission electron microscopy highlight the necessity of the fabrication step to achieve high-performance contacts as no PdSex forms, and WSe2 is unperturbed by room temperature Pd deposition. However, at least one WSe2 layer is consumed by the necessary interface reactions that form PdSex requiring strategic exploitation of a sacrificial WSe2 layer during device fabrication. The interface chemistry and structural properties are correlated with Pd–WSe2 diode and transistor performance, and the recommended processing steps are provided to enable reliable high-performance contact formation.

Hot carrier stress, where the gate and drain voltages were stressed simultaneously, was executed on ZnO thin-film transistors (TFTs) with different PLD ZnO or ALD Al2O3 deposition parameters. The threshold voltage and transconductance were monitored where 30 mTorr samples had greater threshold voltage shifts and transconductance $(\mathrm{g}_{\mathrm{m}})$ degradation compared to the 20 mTorr ZnO film. For samples with and without a 400°C forming gas anneal, greater degradation was seen in the annealed sample, which indicates 400°C may be too aggressive. The correlation between $\mathrm{g}_{\mathrm{m}}$ degradation (i.e., interface degradation) and $\Delta \mathrm{V}_{\mathrm{t}}$ demonstrate that there is influence to the Vt shift from electrically active defects generated in the interfacial region.

The influence of the fabrication process on the electrical performance of ZnO and MoS 2 devices are evaluated due to their promise for future internet of things technology applications beyond silicon. Low temperature processing of gate dielectrics introduce new challenges in obtaining optimal device performance. HfO 2 and Al 2 O 3 gate dielectrics on ZnO or MoS 2 semiconducting layers are electrically characterized to gain understanding of the influence process-induced effects have on transistor performance.

In this study, we investigated the ferroelectric properties of Hf0.5Zr0.5O2 (HZO) thin films with different thicknesses (5-20 nm) deposited by atomic layer deposition for the development of future ferroelectric random access memory cells. HZO-based capacitors with a thickness of 5 nm exhibited a switching polarization of ~13 μC/cm2 and a ferroelectric saturation voltage of ~1.0 V as extracted from the pulse write/read measurements. Furthermore, we performed fatigue measurements and we found no degradation up to 1010 switching cycles at 1.2 V.

We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin $(25~\mu{\rm m})$ silicon fabric which is peeled off using a CMOS compatible process from a standard bulk mono-crystalline silicon substrate. A lifetime projection is extracted using statistical analysis of the ramping voltage $({\rm V}_{\rm ramp})$ breakdown and time dependent dielectric breakdown data. The obtained flexible MOSCAPs operational voltages satisfying the 10 years lifetime benchmark are compared to those of the control MOSCAPs, which are not peeled off from the silicon wafer.

The electronic properties of the HfO

The electronic properties of the HfO2/MoS2 interface were investigated using multifrequency capacitance–voltage (C–V) and current–voltage characterization of top-gated MoS2 metal–oxide–semiconductor field effect transistors (MOSFETs). The analysis was performed on few layer (5–10) MoS2 MOSFETs fabricated using photolithographic patterning with 13 and 8 nm HfO2 gate oxide layers formed by atomic layer deposition after in-situ UV-O3 surface functionalization. The impedance response of the HfO2/MoS2 gate stack indicates the existence of specific defects at the interface, which exhibited either a frequency-dependent distortion similar to conventional Si MOSFETs with unpassivated silicon dangling bonds or a frequency dispersion over the entire voltage range corresponding to depletion of the HfO2/MoS2 surface, consistent with interface traps distributed over a range of energy levels. The interface defects density (Dit) was extracted from the C–V responses by the high–low frequency and the multiple-frequency extraction methods, where a Dit peak value of 1.2 × 1013 cm–2 eV–1 was extracted for a device (7-layer MoS2 and 13 nm HfO2) exhibiting a behavior approximating to a single trap response. The MoS2 MOSFET with 4-layer MoS2 and 8 nm HfO2 gave Dit values ranging from 2 × 1011 to 2 × 1013 cm–2 eV–1 across the energy range corresponding to depletion near the HfO2/MoS2 interface. The gate current was below 10–7 A/cm2 across the full bias sweep for both samples indicating continuous HfO2 films resulting from the combined UV ozone and HfO2 deposition process. The results demonstrated that impedance spectroscopy applied to relatively simple top-gated transistor test structures provides an approach to investigate electrically active defects at the HfO2/MoS2 interface and should be applicable to alternative TMD materials, surface treatments, and gate oxides as an interface defect metrology tool in the development of TMD-based MOSFETs.