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The mass production of photovoltaic (PV) devices requires fast and reliable characterization methods and equipment. PV manufacturers produce a complete module roughly every 20 s, and the electrical performance assessment is typically completed in less than 1 s. Times are even more stringent during cell manufacturing. To be competitive in the PV market, perovskite solar cells and modules aim to the same target, i.e., fast and reliable quality assessment. This communication report discusses the limit of characterizing the current perovskite technology. Standard current vs voltage measurements are compared to maximum power point tracking (MPPT), and a fast MPPT procedure is developed to meet the highly demand standard for quality control in the industry of PV production. [ABSTRACT FROM AUTHOR]

Organic field‐effect transistors (OFETs) are considered almost purely interfacial devices with charge current mainly confined in the first two semiconducting layers in contact with the dielectric with no active role of the film thickness exceeding six to eight monolayers (MLs). By a combined electronic, morphological, structural, and theoretical investigation, it is demonstrated that the charge mobility and source–drain current in 2,20‐(2,20‐bithiophene‐5,50‐diyl)bis(5‐butyl‐5H‐thieno[2,3‐c]pyrrole‐4,6)‐dione (NT4N) organic transistors directly correlate with the out‐of‐plane domain size and crystallite orientation in the vertical direction, well beyond the dielectric interfacial layers. Polycrystalline films with thickness as high as 75 nm (≈30 MLs) and 3D molecular architecture provide the best electrical and optoelectronic OFET characteristics, highlighting that the molecular orientational order in the bulk of the film is the key‐enabling factor for optimum device performance. X‐ray scattering analysis and multiscale simulations reveal the functional correlation between the thickness‐dependent molecular packing, electron mobility, and vertical charge distribution. These results call for a broader view of the fundamental mechanisms that govern field‐effect charge transport in OFETs beyond the interfacial 2D paradigm and demonstrate the unexpected role of the out‐of‐plane domain size and crystallite orientation in polycrystalline films to achieve optimum electronic and optoelectronic properties in organic transistors. [ABSTRACT FROM AUTHOR]

Costs and toxicity concerns are at the center of a heated debate regarding the implementation of perovskite solar cells (PSCs) into commercial products. The first bottleneck could be overcome by eliminating the top metal electrode (generally gold) and the underlying hole transporting material and substituting both with one single thick layer of conductive carbon, as in the so‐called carbon‐based PSCs (C‐PSCs). The second issue, related to the presence of lead, can be tackled by resorting to other perovskite structures based on less toxic metallic components. An interesting case is that of the double perovskite Cs2AgBiBr6, which at present still lacks the outstanding optoelectronic performances of the lead‐based counterparts but is very stable to environmental factors. In this work, the processing of carbon electrodes onto Cs2AgBiBr6‐based C‐PSCs was reported, starting from an additive‐free isopropanol ink of a carbon material obtained from the hydrothermal recycling of waste tires and employing a high‐throughput ultrasonic spray coating method in normal environmental conditions. Through this highly sustainable approach that ensures a valuable step from an end‐of‐life to an end‐of‐waste status for used tires, devices were obtained delivering a record open circuit voltage of 1.293 V, which might in the future represent ultra‐cheap solutions to power the indoor Internet of Things ecosystem. [ABSTRACT FROM AUTHOR]

We investigate Ferroelectric Random Access Memories subjected to X-ray and proton irradiations. We address the radiation damage dependence on irradiation temperature, its stability during annealing and cycling, and the effects of supply voltage and packaging. The radiation damage strongly depends on the irradiation temperature. Immediately after proton or X-ray irradiation, we detect only stuck bits without data corruption, at least at doses up to 9 Mrad(Si) at room temperature. The radiation damage anneals in time as long as several weeks, and the recovery rate is accelerated by either electrical cycling or high temperature annealing. The radiation tolerance is much higher if the device is irradiated unpowered. Finally, we present a degradation model that accounts for the irradiation temperature dependence. Index Terms--CMOS memory integrated circuits, ferroelectric capacitors, ferroelectric memories, radiation effects, random access memories, semiconductor memories.

We compared the radiation tolerance of nanocrystal and floating gate memories, fabricated with the same technology. We investigated the effects of 5-MeV proton and 10-keV X-Ray irradiations, focusing on the charge loss, the permanent degradation of the electrical characteristics, and the data retention. We also presented a first order model of the charge loss and the permanent threshold voltage shift. The model and the experimental results show that nanocrystal memories feature improved radiation robustness against total ionizing dose. Nanocrystal memories can withstand a radiation dose 3 and 10 times larger than floating gate memories, in terms of charge loss and data retention, respectively. Index Terms--CMOS memory integrated circuits, flash memories, radiation effects, semiconductor devices reliability, semiconductor memories.

We present the first charge loss model of heavy ion induced radiation damage on nanocrystal memory cells. The model takes into account the nanocrystal distribution non uniformity and the effect of different programming techniques, which may produce non uniform charging of the nanocrystals. The model has been validated with a focused microbeam test. It provides an estimation of both the ion track size and the average number of ion hits required for achieving a given charge loss. In our irradiation experiments we estimated an ion track size (diameter) of 85 nm for 50-MeV Cu ions. This model confirms also the good robustness of nanocrystal memories against heavy ion irradiation and their much stronger tolerance than the conventional floating gate based memories. Index Terms--CMOS memory integrated circuits, flash memories, heavy ion irradiation, radiation effects, semiconductor device reliability, semiconductor memories.

We study the immediate and long-term effects of heavy-ion strikes on 65-nm Fully Depleted SOI MOSFETs with different strain engineering solutions. Some of the phenomena already present in bulk devices, such as drain current collapse, are still observed alongside some new long-term effects concerning the degradation kinetics under electrical stress. On the other side, early breakdown seems to vanish. SOI degradation after heavy-ion strikes and during following electrical stress is shown to depend on the strain level and strain-inducing technique. We interpreted these results in terms of radiation-induced defects in the gate and isolation oxide. Index Terms--CMOS devices and integrated circuits reliability, heavy ions, SOI, strain.

We present new results on heavy-ion irradiation of nanocrystal non-volatile addressable memory arrays. We show that the effects of a single ion hit are negligible on these devices due to the discrete nature of the storage sites. We estimate that, in order to observe an appreciable threshold voltage shift, at least three to four ion hits are needed. Despite several cells experiencing multiple hits they are still functional after the irradiation, showing no changes on the retention characteristics. These results highlight an outstanding improvement of the nanocrystal technology over the conventional floating gate memories in terms of radiation tolerance, which are encouraging for a potential application in radiation harsh environments. Index Terms--CMOS memory integrated circuits, heavy ion irradiation, radiation effects, semiconductor device reliability, semiconductor memories.

We present new results on electrostatic discharges in fully depleted SOI MOSFETs struck by heavy ions. We investigate the sensitivity of irradiated MOSFETs to discharges applied both at the gate and drain terminals. A single heavy-ion strike is shown to reduce the ESD breakdown voltage and enhance the probability of generating source-drain filaments for gate ESD events, while leaving the sensitivity to drain events unchanged. Radiation-induced latent damage in the gate oxide and defects in the silicon body are pointed out as possible reasons for the modified response to electrostatic discharges after irradiation. Index Terms--CMOS, ESD, radiation effects, SOI.

We investigate heavy ion irradiation effects on large area capacitors with an Oxide-Nitride-Oxide (ONO) stack as dielectric. Despite the thickness of this stack (16.5 nm), we observe the onset of a leakage current after irradiation. We demonstrate that this leakage current is a truly DC current that flows through the ONO stack and decreases with time. Electrical stresses demonstrate that irradiation does not reduce the time-to-breakdown of these devices. Noticeably, capacitors with a 9-nm Si[O.sub.2] layer as dielectric and irradiated with the same ion specie and with the same fluence do not show any measurable leakage current. Index Terms--Flash memories, floating gate memories, heavy-ion, nitride, ONO, radiation effects, radiation induced leakage current.

Proton irradiation of nanocrystals memories produces peculiar radiation effects on the electrical characteristics of these devices, owing to their thin tunnel oxide and to the presence of nanocrystals replacing the conventional flash memory floating gate. In this work, we show that the data retention capability is compromised only after high fluences and that irradiated devices do not show accelerated degradation during subsequent electrical stresses. The presence of nanocrystals instead of a floating gate reduces also the quantity of charge lost during irradiation, indicating these devices as possible candidates for space and avionic environments. Index Terms--CMOS memory integrated circuits, nonvolatile memories, proton irradiation, radiation effects.

We present new original experimental results on the effects produced by single heavy-ion strikes on minimum-size MOSFETs manufactured in a 0.1-[micro]m CMOS technology. We show that, whereas large-width samples do not suffer from any particular degradation when struck by a single ion, minimum size devices, which are the real building block of modern digital circuits, display small but significant changes in the electrical characteristics. In particular, we identify and classify the different types of degradation occurring after irradiation with high-LET particles and attribute them to ion strikes occurring in different parts of the MOSFET: gate oxide, LDD spacers, and STI. Even though the observed changes do not compromise the device functionality, they clearly indicate that, as the feature size is scaled into the decananometer range, single heavy-ion strikes will have a growing effect on digital circuits. Index Terms--CMOS, heavy ions.

In this work we focused our attention on heavy ion irradiation effects on nanocrystal memory cell arrays. All cells are fabricated by depositing Si nanocrystai on top of a Si[O.sub.2] layer. Immediately after irradiation we observed neither charge loss following the ion hit, nor appreciable change of the electrical characteristics of the nanocrystai MOSFETs, such as transconductance and drain current decrease. In addition, despite the gate oxide leakage current may show a large increase after irradiation with high energy ions, the data retention time of the cells is not compromised, due to the discrete nature of the nanocrystal storage node. Index Terms--CMOS memory integrated circuits, heavy ion irradiation, non-volatile memories, radiation effects.

We studied the response of a commercial 0.13-[micro]m CMOS technology to high-energy (24-GeV) proton irradiation, which emulated the environment the front-end electronics of future high-energy accelerators will have to operate in, for fluences up to [10.sup.16] p/[cm.sup.2]. After irradiation, large negative shifts in the threshold voltage and large drops in the maximum transconductance were observed in PMOSFETs, whereas comparatively smaller effects were present in NMOSFETs. Furthermore, both kinds of devices exhibited an increase in the drain off-current and in the gate leakage current. All the observed effects were roughly proportional to the proton fluence. For the PMOSFETs only, the amount of the degradation depended on the device channel length. The changes in the characteristics of the irradiated devices were attributed to the build-up of positive charge in the LDD spacer oxide and to the creation of defects in the gate oxide. Index Terms--CMOS, high-energy physics experiments, ultra-thin gate oxides.

We present the first experimental data about the wear-out of a 0.1 [micro]m partially depleted SOI CMOS technology after heavy ion irradiation. We show that accelerated life tests based on high electric fields yield significant differences between irradiated and nonirradiated devices, even though no or only minor changes are visible in the characteristics of the devices after irradiation. First, the time to breakdown of the front gate oxide is significantly lower in the irradiated samples. The fresh devices experienced breakdown after 5-8 x [10.sup.22] electrons/[cm.sup.2] were injected across the oxide during high field electrical stress. In the irradiated oxide, the breakdown was reached at much lower injected charge values, between 0.5 x [10.sup.22] electrons/[cm.sup.2] and 1.5-1 x [10.sup.22] electrons/[cm.sup.2] depending on the ion fluences. This translates into a lifetime reduction of 10%-20% of its initial value. Furthermore, the degradation kinetics of the threshold voltage and transconductance peak are strongly affected by ion strikes. In particular, a sudden shift of the threshold voltage and an acceleration in the degradation of the transconductance peak were observed upon the application of an electrical stress, which have no correspondence in nonirradiated devices. An acceleration in the degradation of the parasitic back transistor was observed as well. These phenomena were interpreted in terms of latent damage left by the irradiation in the oxides that make up SOI devices. Index Terms--CMOS devices and integrated circuits reliability, gate oxide reliability, radiation effects on MOSFETs, silicon on insulator.

In this work, we have focused our attention on MOSFETs, which are the real basic elements of all CMOS applications. We have studied the immediate and latent effects produced by heavy ion irradiation on MOSFETs with ultrathin gate oxide, even after electrical stresses subsequent to irradiation. We found that a single ion can generate a physically damaged region (PDR) localized in the Si-Si[O.sub.2] interface, which may hamper the surface channel formation. In order to generate a PDR the ion hit must be close enough to MOSFET borders, i.e., in correspondence with the STI or the LDD spacer. Consequently, if both MOSFET W and L are large enough only few ion hits may give place to a PDR, mitigating the radiation damage. Finally we have developed an original model to describe the impact of the PDR on channel conductance in the ohmic linear region. On the basis of this model, we predicte a PDR size around 0.2-1 [micro]m.

In this work, we present an original model to explain the accelerated wear-out behavior of irradiated ultra-thin oxides. The model uses a statistical approach to the breakdown occurrences based on a nonhomogeneous Poisson process. By means of our model, we can estimate the number and the time evolution of those damaged regions produced by ion hits that generate breakdown spots during high field stresses after irradiation, including the dependence on the oxide field. Also, by using the proposed model, we have studied the wear-out dependence on the stress voltage, gate area, and ion fluence. In particular, by studying the stress voltage dependence of wear-out acceleration, it is feasible to extrapolate the device lifetime even at low operating voltage. Index Terms--Accelerated breakdown, CMOS devices reliability, nonhomogeneous Poisson process, radiation stresses, thin oxide reliability.

We have investigated how ultra-thin gate oxides subjected to heavy ion irradiation react to a subsequent electrical stress performed at low voltages. Even in devices exhibiting small (or even no) increase of the gate current after irradiation, the time-to-breakdown is substantially reduced in comparison with unirradiated samples due to the onset of a soft or hard breakdown, in contrast with previous results found on thicker oxides. In fact, we have demonstrated that the radiation damage acts as a seed for further oxide degradation by electrical stress during the device operating life. The accelerated oxide wear-out depends on the linear energy transfer (LET) coefficient of radiation source. Index Terms--Accelerated breakdown, CMOS devices reliability, radiation stresses, thin oxide reliability.

We have investigated new aspects of the gate leakage current due to radiation-induced soft breakdown (RSB) of thin oxides subjected to heavy-ion irradiation. Temperature and noise characteristics of RSB on MOS capacitors with 3- and 4- nm MOS oxides have been experimentally investigated. We have developed an empirical law to describe quantitatively the temperature dependence of the RSB current. A small activation energy has been found by using an Arrhenius relation, in agreement with the RSB tunneling conduction mechanism. The RSB variation at high temperature has been only estimated, as measurements of RSB oxides easily produced catastrophic breakdown. We have studied the RSB noise and identified different contributions to the characteristic random telegraph noise, correlated with the trapping and conduction characteristics of the RSB spots. An original model has been developed that successfully describes the different probability distributions of the current fluctuations that cannot be simulated by using previous models, such as those based on L6vy or Gaussian distributions. Finally, a correlation was established between the shape of the fluctuation distribution and the degradation level of the oxide. Index Terms--Noise in MOS devices, oxide reliability, radiation soft breakdown, radiation stresses.