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Summary: Cascode HEMTs exhibit high gain and broadband performance. Promising reverse transmission makes matching networks simpler and insensitive to impedance on either side of the HEMT. On the other hand, common source (CS) HEMTs with intentional small inductance at the source provide simultaneous match for optimum noise and input impedance. This paper provides a performance comparison of 4×50 μm cascode HEMTs‐based low‐noise amplifier and 4×50 μm CS HEMTs‐based low‐noise amplifiers with specific emphasis on robustness, including survivability and reverse recovery time (RRT). Cascode LNA survives an input power of 33 dBm while CS LNA handles 30 dBm power, each having a 1 k Ω passive limiting resistor on the gate bias line. RRT of cascode LNA is also better. Better survivability and RRT for cascode LNA are attributed to its HEMT's stacked configuration. The designs of LNAs are described, along with their small‐signal, noise, and large‐signal characteristics in the X‐band. Cascode LNA has a better input match, while CS LNA has a better output match. Gains are comparable, while CS LNA has better P1dB at higher band edge frequency. The noise figure for both LNAs is less than 1.9 dB, with CS LNA having a slight edge over cascode. This study benefits RF designers in choosing appropriate HEMT topology as per application for designing robust low‐noise amplifiers. [ABSTRACT FROM AUTHOR]

A cross-coupled cascode feedback design for a frequency compensated operational transconductance amplifier (OTA) is presented here. This OTA is able to achieve a power supply rejection ratio (PSRR) 93 dB (DC) and common mode rejection ratio (CMRR) 41.41 dB (DC) with very low value of compensation capacitors 0.1pF driving a large load of 400pF||2.2kΩ. The proposed OTA design is simulated in 180 nm technology using Electric VLSI tool for validating its performance. The simulated results, PSRR 93 dB at 1 kHz, 83.42 dB at 1 MHz, 71.23 dB at 1 GHz are noted. Further simulated results, CMRR 41.41 dB at 1 kHz, 41.97 dB at 1 MHz and 70.79 dB at 1 GHz are also observed. Small signal and transient performances are analyzed and post-layout simulations bring out the following results: DC gain of 43.21 dB, unity-gain-frequency (UGF) of 27 MHz, Phase Margin of 48.50, slew-rate (+) of 4.63 V/μs and slew-rate (−) of 1.00 V/μs. Additionally, the circuit occupies an area of 0.014 mm 2 and the power consumption observed is 3.17 mW. [ABSTRACT FROM AUTHOR]

This article presents the design of a low-power low noise amplifier (LNA) implemented in 45 nm silicon-on-insulator (SOI) technology using the g m / I D methodology. The Ka-band LNA achieves a very low power consumption of only 1.98 mW andis the first time the g m / I D approach is applied at such a high frequency. The circuit is suitable for Ka-band applications with a central frequency of 28 GHz, as the circuit is intended to operate in the n257 frequency band defined by the 3GPP 5G new radio (NR) specification. The proposed cascode LNA uses the g m / I D methodology in an RF/MW scenario to exploit the advantages of moderate inversion region operation. The circuit occupies a total area of 1.23 mm2 excluding pads and draws 1.98 mW from a DC supply of 0.9 V. Post-layout simulation results reveal a total gain of 11.4 dB, a noise figure (NF) of 3.8 dB, and an input return loss (IRL) better than 12 dB. Compared to conventional circuits, this design obtains a remarkable figure of merit (FoM) as the LNA reports a gain and NF in line with other approaches with very low power consumption. [ABSTRACT FROM AUTHOR]

This paper presents a high-gain low-noise amplifier (LNA) operating at the 5G mm-wave band. The full design combines two conventional cascode stages: common base (CB) and common emitter (CS). The design technique reduces the miller effect and uses low-voltage supply and low-current-density transistors to simultaneously achieve high gain and low noise figures (NFs). The two-stage LNA topology is analyzed and designed using 0.25 µm SiGe BiCMOS process technology from NXP semiconductors. The measured circuit shows a small signal gain at 26 GHz of 26 dB with a gain error below 1 dB on the entire frequency band (26–28 GHz). The measured average NF is 3.84 dB, demonstrated over the full frequency band under 15 mA current consumption per stage, supplied with a voltage of 3.3 V. [ABSTRACT FROM AUTHOR]

This paper presents a power amplifier for synthetic aperture radar transmitters using the Ka-band and a 40-nm CMOS process. The designed amplifier consists of two stages: A driver amplifier in the first stage and a power amplifier in the second stage. The driver amplifier employs a differential common-source amplifier, whereas the power amplifier is designed using a differential cascode amplifier. To ensure the stability of the amplifiers, both the driver and power amplifiers utilize neutralization techniques that utilize capacitors. The input of the driver amplifier was matched using a single-to-differential balun, whereas interstage matching between amplifiers was achieved using transformers. The power amplifier output is matched for power optimization using a differential-to-single balun. The output power of the power amplifier is 16.9 dBm, consuming 351 mW of power. The center frequency of output power is 34 GHz, with a 1 dB bandwidth ranging from 28.1 to 39.8 GHz. The total area, including the DC and input/output pads, was 711 μm×504 μm [ABSTRACT FROM AUTHOR]

This article presents the design of a low-power low noise amplifier (LNA) implemented in 45 nm silicon-on-insulator (SOI) technology using the gm/ID methodology. The Ka-band LNA achieves a very low power consumption of only 1.98 mW andis the first time the gm/ID approach is applied at such a high frequency. The circuit is suitable for Ka-band applications with a central frequency of 28 GHz, as the circuit is intended to operate in the n257 frequency band defined by the 3GPP 5G new radio (NR) specification. The proposed cascode LNA uses the gm/ID methodology in an RF/MW scenario to exploit the advantages of moderate inversion region operation. The circuit occupies a total area of 1.23 mm2 excluding pads and draws 1.98 mW from a DC supply of 0.9 V. Post-layout simulation results reveal a total gain of 11.4 dB, a noise figure (NF) of 3.8 dB, and an input return loss (IRL) better than 12 dB. Compared to conventional circuits, this design obtains a remarkable figure of merit (FoM) as the LNA reports a gain and NF in line with other approaches with very low power consumption.

This paper presents a high-gain low-noise amplifier (LNA) operating at the 5G mm-wave band. The full design combines two conventional cascode stages: common base (CB) and common emitter (CS). The design technique reduces the miller effect and uses low-voltage supply and low-current-density transistors to simultaneously achieve high gain and low noise figures (NFs). The two-stage LNA topology is analyzed and designed using 0.25 µm SiGe BiCMOS process technology from NXP semiconductors. The measured circuit shows a small signal gain at 26 GHz of 26 dB with a gain error below 1 dB on the entire frequency band (26–28 GHz). The measured average NF is 3.84 dB, demonstrated over the full frequency band under 15 mA current consumption per stage, supplied with a voltage of 3.3 V.

This paper presents a 250 kHz bidirectional battery charger circuit using a GaN HEMT. The charger is subjected to a high-/low-side constant voltage at 200 V/20 V. The charger circuit is a hybrid of the LLC and flyback circuit topologies. Both the power output analysis and efficiency control of this circuit are simplified when the magnetization current is minimized using the low-resistance GaN HEMT. The switching frequency is controlled to match the series resonance in a way that is analogous to conventional LLC circuit controls, while the duty ratio that determines the power output and the dead time, which determines the zero voltage switching, is controlled in an analogous manner to the flyback circuit control. The charging and discharging modes were altered by applying a double-throw relay that changes the transformer turn ratio, which is different from conventional LLC designs using the switching frequency adjustment. A nominal turn ratio with Np = 35 and Ns = 3.5 for a 200 V/20 V converter can only produce an internal series resonance with no current flowing in any charging direction. The proposed circuit using a transformer with multiple windings (Np = 35, Ns,F = 4, and Ns,R = 3) was fabricated to deliver 125 W output power from the power grid battery to the vehicle battery in the forward (charging) mode and 90 W in the reverse (discharging) mode. The conversion efficiency was calculated to be as high as 97% in the forward mode and 95% in the reverse mode. The high conversion efficiency is due to the characteristics of the GaN HEMT, including low resistive and switching losses. The equations derived in this paper associate these losses with the series resonant frequency and power conversion rate, which highlight the advantages of using a GaN HEMT in this CLLC design. [ABSTRACT FROM AUTHOR]

In this work, the design of a wideband low-noise amplifier (LNA) using a resistive feedback network is proposed for potential multi-band sensing, communication, and radar applications. For achieving wide operational bandwidth and flat in-band characteristics simultaneously, the proposed LNA employs a variety of circuit design techniques, including a voltage–current (shunt–shunt) negative feedback configuration, inductive emitter degeneration, a main branch with an added cascode stage, and the shunt-peaking technique. The use of a feedback network and emitter degeneration provides broadened transfer characteristics for multi-octave coverage and a real impedance for input matching, respectively. In addition, the cascode stage pushes the band-limiting low-frequency pole, due to the Miller capacitance, to a higher frequency. Lastly, the shunt-peaking approach is optimized for the compensation of a gain reduction at higher frequency bands. The wideband LNA proposed in this study is fabricated using a commercial 0.13 μm silicon-germanium (SiGe) BiCMOS process, employing SiGe heterojunction bipolar transistors (HBTs) as the circuit's core active elements in the main branch. The measurement results show an operational bandwidth of 2.0–29.2 GHz, a noise figure of 4.16 dB (below 26.5 GHz, which was the measurement limit), and a total power consumption of 23.1 mW under a supply voltage of 3.3 V. Regarding the nonlinearity associated with large-signal behavior, the proposed LNA exhibits an input 1-dB compression (IP1dB) point of −5.42 dBm at 12 GHz. These performance numbers confirm the strong viability of the proposed approach in comparison with other state-of-the-art designs. [ABSTRACT FROM AUTHOR]

This paper describes a low power, low phase noise CMOS voltage controlled oscillator (VCO) with a cascoded cross-coupled pair (XCP) configuration for high data rate 5G New Radio (5G-NR) applications. The core consists of a primary auxiliary VCO built as a negative conductance circuit to improve phase noise and a secondary core with a cascoded formation to increase output voltage swing. A switched varactor array (SVA) wideband tuner is integrated for a wide bandwidth application in a low power implementation. The dual-core VCO was designed in CMOS 130 nm technology and occupies only 1.05 mm2 of space. With a supply voltage of 1.2 V, the VCO achieved a tuning range of 32.43% from 3.45 GHz to 4.47 GHz. At 3.96 GHz carrier center frequency with 1 MHz offset, the total power consumption is 0.7 mW with a corresponding phase noise (PN) of -121.25 dBc/Hz and a Figure of Merit (FoM) of 193.25 dBc/Hz. The results are validated using Cadence Spectra RF simulations. [ABSTRACT FROM AUTHOR]

Copyright of Electronic Components & Materials is the property of Electronic Components & Materials and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

High-electron-mobility transistors based on gallium nitride technology are the most recently developed power electronics devices involved in power electronics applications. This article critically overviews the advantages and drawbacks of these enhanced, wide-bandgap devices compared with the silicon and silicon carbide MOSFETs used in power converters. High-voltage and low-voltage device applications are discussed to indicate the most suitable area of use for these innovative power switches and to provide perspective for the future. A general survey on the applications of gallium nitride technology in DC-DC and DC-AC converters is carried out, considering the improvements and the issues expected for the higher switching transient speed achievable. [ABSTRACT FROM AUTHOR]

This paper presents a 160 GHz, D-band, low-noise amplifier (LNA) and a D-band power amplifier (PA) implemented in the Global Foundries 22 nm CMOS FDSOI. The two designs are used for the contactless monitoring of vital signs in the D-band. The LNA is based on multiple stages of a cascode amplifier topology with a common source topology adopted as the input and output stages. The input stage of the LNA is designed for simultaneous input and output matching, while the inter-stage-matching networks are designed for maximizing the voltage swing. The LNA achieved a maximum gain of 17 dB at 163 GHz. The input return loss was quite poor in the 157–166 GHz frequency band. The −3 dB gain bandwidth corresponded to 157–166 GHz. The measured noise figure was between 7.6 dB and 8 dB within the −3 dB gain bandwidth. The power amplifier achieved an output 1 dB compression point of 6.8 dBm at 159.75 GHz. The measured power consumptions of the LNA and the PA were 28.8 mW and 10.8 mW, respectively. [ABSTRACT FROM AUTHOR]

In this paper, we present a W-band power amplifier using a 28-nm CMOS process for radar applications. The designed amplifier consists of a two-stage driver amplifier and last-stage power amplifier. The driver amplifier uses a differential common-source topology, and the power amplifier adopts a differential cascode topology. Both the driver amplifier and power amplifier utilize the neutralization technique at the common-source stage for stability and sufficient power gain. Each interstage of the amplifier used a transformer for impedance matching. The W-band signal applied to the first driving amplifier is supplied 14 GHz to 16 GHz external signal source multiplied by 6 using the internal multiplier, the power amplifier achieved 14.9 dBm output power, and the 3-stage amplifier consumed 262 mW of DC power. The 1 dB-bandwidth is 10 GHz from 85 GHz to 95 GHz. The core size of the 3-stage amplifier is 110 μm ⨯ 300 μm. [ABSTRACT FROM AUTHOR]

This letter presents a 39-GHz phase-inverting variable gain power amplifier (VGPA) for 5G communication. Adopting a Gilbert structure-based variable gain amplifier (VGA) stage, the VGPA realized the dB-linear gain control characteristic as well as 180° phase inversion. At 0°/180° phase states, the 39-GHz VGPA achieves the maximum gain of 38.7/38.9 dB with gain tuning range of 5.6/5.2 dB, respectively. Over 38–43 GHz, the phase inversion error is limited within 5.9°, and the rms phase error is less than 3.6°/2.2°. Meanwhile, with the metal interleaving coplanar transformer matching network, this VGPA achieves 17.7/17.6-dBm Psat and 13.2/13.36-dBm OP1 dB, with the power added efficiency (PAE) of 35%/34.5% and 13.6%/14.4% at the saturation and 1-dB compression points, respectively. Over the gain control states, the OP1 dB fluctuation is less than 0.3 dB. Implemented in a 65-nm CMOS process, the proposed VGPA consumes 150 mW with a chip area of 0.3 mm2. [ABSTRACT FROM AUTHOR]

With the increase in renewable energy generation, microgrid has put forward higher requirements on the power density and performance of the photovoltaic inverter. In this paper, the dynamic process of inverter based on the cascode Gallium nitride (GaN) high electron mobility transistor (HEMT) for the photovoltaic (PV) application is analyzed in detail. The parasitic inductors and capacitors have been considered in our proposed equivalent model, which can explain the phenomenon that the crossover time of the voltage and current is prolonged by the parasitic parameters. The influence of the parasitic parameters is identified through theoretical analysis. By analyzing the influence of parasitic parameters, the design process of high-frequency inverter can be optimized. A 500 W inverter based on the cascode GaN HEMT is built, and the correctness of theoretical and simulation analysis is verified by the experimental results. [ABSTRACT FROM AUTHOR]

This paper presents a multi-band low-noise amplifier (LNA) in the 45-nm CMOS silicon-on-insulator (SOI) process. The LNA consists of three stages, with the differential cascode amplifier as the core structure. The first stage is mainly responsible for input matching to ensure favourable noise characteristics and bandwidth, while the subsequent stages increase the gain. Moreover, the LNA utilizes baluns for input/output and interstage impedance matching. Switch capacitances are added to switch the three operating bands of the LNA, which cover 17–38 GHz overall. Measurement results show that the proposed LNA achieves a gain (S21) of 23.0 dB and a noise figure (NF) of 4.0 dB. [ABSTRACT FROM AUTHOR]

This paper presents a 250 kHz bidirectional battery charger circuit using a GaN HEMT. The charger is subjected to a high-/low-side constant voltage at 200 V/20 V. The charger circuit is a hybrid of the LLC and flyback circuit topologies. Both the power output analysis and efficiency control of this circuit are simplified when the magnetization current is minimized using the low-resistance GaN HEMT. The switching frequency is controlled to match the series resonance in a way that is analogous to conventional LLC circuit controls, while the duty ratio that determines the power output and the dead time, which determines the zero voltage switching, is controlled in an analogous manner to the flyback circuit control. The charging and discharging modes were altered by applying a double-throw relay that changes the transformer turn ratio, which is different from conventional LLC designs using the switching frequency adjustment. A nominal turn ratio with Np = 35 and Ns = 3.5 for a 200 V/20 V converter can only produce an internal series resonance with no current flowing in any charging direction. The proposed circuit using a transformer with multiple windings (Np = 35, Ns,F = 4, and Ns,R = 3) was fabricated to deliver 125 W output power from the power grid battery to the vehicle battery in the forward (charging) mode and 90 W in the reverse (discharging) mode. The conversion efficiency was calculated to be as high as 97% in the forward mode and 95% in the reverse mode. The high conversion efficiency is due to the characteristics of the GaN HEMT, including low resistive and switching losses. The equations derived in this paper associate these losses with the series resonant frequency and power conversion rate, which highlight the advantages of using a GaN HEMT in this CLLC design.

In this work, the design of a wideband low-noise amplifier (LNA) using a resistive feedback network is proposed for potential multi-band sensing, communication, and radar applications. For achieving wide operational bandwidth and flat in-band characteristics simultaneously, the proposed LNA employs a variety of circuit design techniques, including a voltage–current (shunt–shunt) negative feedback configuration, inductive emitter degeneration, a main branch with an added cascode stage, and the shunt-peaking technique. The use of a feedback network and emitter degeneration provides broadened transfer characteristics for multi-octave coverage and a real impedance for input matching, respectively. In addition, the cascode stage pushes the band-limiting low-frequency pole, due to the Miller capacitance, to a higher frequency. Lastly, the shunt-peaking approach is optimized for the compensation of a gain reduction at higher frequency bands. The wideband LNA proposed in this study is fabricated using a commercial 0.13 μm silicon-germanium (SiGe) BiCMOS process, employing SiGe heterojunction bipolar transistors (HBTs) as the circuit’s core active elements in the main branch. The measurement results show an operational bandwidth of 2.0–29.2 GHz, a noise figure of 4.16 dB (below 26.5 GHz, which was the measurement limit), and a total power consumption of 23.1 mW under a supply voltage of 3.3 V. Regarding the nonlinearity associated with large-signal behavior, the proposed LNA exhibits an input 1-dB compression (IP1dB) point of −5.42 dBm at 12 GHz. These performance numbers confirm the strong viability of the proposed approach in comparison with other state-of-the-art designs.

This paper reviewed the state-of-the-art wide band-gap (WBG) technology from material level to system level. The properties of semiconductor materials, i.e., silicon carbide and gallium nitride, were investigated. The electrical characteristics of commercial power devices, which include static and dynamic performances, were assessed, and compared. The design requirements of WBG gate drivers were then underpinned, and various gate driver topologies were reviewed. Finally, their implementation in power electronic converters and performances were evaluated. [ABSTRACT FROM AUTHOR]

An efficient, broadband SiGe HBT cascode nonuniform distributed power amplifier (NDPA) is presented for low-cost, fully integrated Si-based phased arrays. Optimum load impedances at each SiGe HBT cascode in a four-stage NDPA core are obtained by scaling the characteristic impedance ($Z_{0}$) of the collector transmission lines (TLs) and tapering the SiGe HBT emitter area simultaneously. A novel compact, lumped-element two-section $\lambda $ /4 output impedance transformer (OIT) is proposed to lower the NDPA load impedance ($Z_{L}$) from 50 to 25 $\Omega $ over more than one decade bandwidth (BW). Each $\lambda $ /4 impedance transformer is realized by four cascaded CLC $\pi $ -networks integrated into a single three-turn symmetric inductor in order to achieve compact size, high passive efficiency, and high LC cutoff frequency ($f_{c}$). The systematic design approach of a lumped-element $\lambda $ /4 impedance transformer with an arbitrary $Z_{0}$ is described in detail. The prototype NDPA was fabricated in 0.13- $\mu \text{m}$ SiGe HBT BiCMOS technology. The proposed SiGe HBT cascode NDPA supports both high linearity (HL) and high gain (HG) modes, each suited to a specific application. The NDPA attains a peak power gain of 10.3/12.5 dB, a saturated output power ($P_{\mathrm {out}}$) of 21.3/21.5 dBm, and a power added efficiency (PAE) of 12.2%/12.5%–21.6%/22.0% for HL/HG modes, with a 3-dB BW from 1.5 to 24.0 GHz. The NDPA delivers 13.0-dBm average $P_{\mathrm {out}}$ with a PAE of 10.0% at 6-Gbit/s data rate 64 QAM modulation. [ABSTRACT FROM AUTHOR]

This paper presents a 160 GHz, D-band, low-noise amplifier (LNA) and a D-band power amplifier (PA) implemented in the Global Foundries 22 nm CMOS FDSOI. The two designs are used for the contactless monitoring of vital signs in the D-band. The LNA is based on multiple stages of a cascode amplifier topology with a common source topology adopted as the input and output stages. The input stage of the LNA is designed for simultaneous input and output matching, while the inter-stage-matching networks are designed for maximizing the voltage swing. The LNA achieved a maximum gain of 17 dB at 163 GHz. The input return loss was quite poor in the 157–166 GHz frequency band. The −3 dB gain bandwidth corresponded to 157–166 GHz. The measured noise figure was between 7.6 dB and 8 dB within the −3 dB gain bandwidth. The power amplifier achieved an output 1 dB compression point of 6.8 dBm at 159.75 GHz. The measured power consumptions of the LNA and the PA were 28.8 mW and 10.8 mW, respectively.

A low output resistance and high slew rate class-AB flipped voltage follower (FVF) cell is presented in this paper. The proposed FVF cell consists of cascoding transistor which provides the extra gain to the feedback loop and leads to the low output resistance while the bulk-driven transistor acts as an adjustable current source to increase the current driving capability and slew rate. The proposed FVF cell offers numerous advantages such as low output resistance, high current driving capability, wide bandwidth, high symmetrical slew rate and occupies less chip area. The proposed circuit has been designed using Cadence virtuoso tool in 0.18 µm CMOS technology and the post-layout simulation results are presented to validate its performance. To show the performance under extreme conditions, the analysis of the proposed circuit at various corners has also been presented. [ABSTRACT FROM AUTHOR]

Copyright of Electronic Components & Materials is the property of Electronic Components & Materials and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This study introduces the design of an RF CMOS power amplifier based on a cascode powercell. self-body-biasing (SBB) of common source (CS) transistors (TRs) was proposed to improve the nonlinearity of power amplifiers. Accordingly, an analysis of the linearization principle of SBB was performed through simulation. The SBB technique is configured by inserting a 4 kΩ resistor between the body and the drain of the CS TRs. Accordingly, using the SBB to the CS TRs could achieve the effect of reducing the third-order intermodulation distortions (IMD3) by changing the third-order transconductance (gm3). Moreover, an effect of reducing AM-PM distortions could be achieved by securing a voltage condition in which the CG TRs could operate in a saturation region, which reduces the variation of parasitic capacitances at the output terminal. [ABSTRACT FROM AUTHOR]

This brief proposes and verifies a new phase shifter applied in the rotated phase tuning (RPT) technique in Ka-band. The flexible phase shift in the RPT technique is significant for avoiding the phase ambiguity issue of oscillating mode and improve the phase noise and tuning range. The proposed common-source-common-gate (CSCG) transistor is simple and can provide a wide range of phase shift for different frequencies. A QVCO without varactor is designed by using a CSCG to replace the common-source (CS) as the negative resistance unit as well as the phase shifter. The negative impedance, tuning range, phase noise and quadrature accuracy of CS and CSCG QVCO are compared and numerically verified using a simulation model. Finally, we further fabricate the CSCG QVCO in a 65-nm CMOS process to verify the accuracy of the simulation model. [ABSTRACT FROM AUTHOR]

Single-photon avalanche diodes (SPADs) have become the sensor of choice in many applications whenever high sensitivity, low noise, and sharp timing performance are required, simultaneously. Recently, SPADs designed in CMOS technology, have yielded moderately good performance in these parameters, but never equaling their counterparts fabricated in highly customized, non-standard technologies. The arguments in favor of CMOS-compatible SPADs were miniaturization, cost and scalability. In this paper, we present the first CMOS SPAD with performance comparable or better than that of the best custom SPADs, to date. The SPAD-based design, fully integrated in 180 nm CMOS technology, achieves a peak photon detection probability (PDP) of 55% at 480 nm with a very broad spectrum spanning from near ultraviolet (NUV) to near infrared (NIR) and a normalized dark count rate (DCR) of 0.2 cps/ $\mu$ m $^2$ , both at 6 V of excess bias. Thanks to a dedicated CMOS pixel circuit front-end, an afterpulsing probability of about 0.1% at a dead time of $\sim$ 3 ns were achieved. We designed three SPADs with a diameter of 25, 50, and 100 $\mu$ m to study the impact of size on the timing jitter and to create a scaling law for SPADs. For these SPADs, a single-photon time resolution (SPTR) of 12.1 ps, 16 ps, and 27 ps (FWHM) was achieved at 6 V of excess bias, respectively. The SPADs operate in a wide range of temperatures, from −65 $^{\circ }$ C to 40 $^{\circ }$ C, reaching a normalized DCR of 1.6 mcps/ $\mu$ m $^2$ at 6 V of excess bias for the 25 $\mu$ m at −65 $^{\circ }$ C. The proposed SPADs are ideal for a wide range of applications, including (quantum) LiDAR, super-resolution microscopy, quantum random number generators, quantum key distribution, fluorescence lifetime imaging, time-resolved Raman spectroscopy, to name a few. All these applications can take advantage of the vastly improved performance of our detectors, while enjoying the opportunities of megapixel resolutions promised by the economy of scale that is offered by CMOS technologies. [ABSTRACT FROM AUTHOR]

This paper presents a 4-way combined G-band power amplifier (PA) fabricated with a 130-nm SiGe BiCMOS process. First, a single-ended PA based on the cascode topology (CT) is designed at 185 GHz, which consists of three stages to get an overall gain and an output power higher than 27 dB and 13 dBm, respectively. Then, a 4-way combiner/splitter was designed using low-loss transmission lines at 130-210 GHz. Finally, the combiner was loaded with four single-ended PAs to complete the design of a 4-way combined PA. The chip of the fabricated PA occupies an area of 1.35mm2. The realized PA shows a saturated output power of 18.1 dBm with a peak gain of 25.9 dB and power-added efficiency (PAE) of 3.5% at 185 GHz. A maximum output power of 18.7 dBm with PAE of 4.4% is achieved at 170 GHz. The 3-dB and 6-dB bandwidth of the PA are 27 and 42 GHz, respectively. In addition, the PA delivers a saturated output power higher than 18 dBm in the frequency range 140-186 GHz. To the best of our knowledge, the power reported in this paper is the highest for G-band SiGe BiCMOS PAs.

A novel sub-5-nm node folded cascode structure using dual workfunction (WF) scheme was proposed using fully-calibrated TCAD. Feasible process flows of the cascode device were adopted from those of nanosheet FETs (NSFETs) and complementary FETs. Key process flows were depositing two different separate spacers and etching one spacer selectively, depositing oxide layer in between source/drain epitaxial growths for electrical isolation, and fill-CMP-etch back sequence for dual-WF. The folded cascode device consists of two or three FETs in series, designated as 2-CAS or 3-CAS respectively, under the same active area. Conventional three-stacked NSFETs have larger transconductance (Gm) than 2-CAS and 3-CAS, but the cascode devices have much larger output resistance (Ro) by dual-WF scheme and thus achieve larger intrinsic gain (AV = GmRo). Smaller Gm and larger gate capacitance for the cascode devices decrease the cutoff frequency. But smaller gate-to-drain capacitance by shrunk drain epi along with large Ro increases the maximum frequency (Fmax). Especially, 2-CAS has larger AV and Fmax than conventional NSFETs for all the NS widths of 20, 30, and 40 nm and at all the operation voltages of 0.6, 0.7, and 0.8 V, promising for low power mobile applications.

Copyright of Electronic Components & Materials is the property of Electronic Components & Materials and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In this paper, a wide-range current mirror based on a low-power flipped voltage follower with improved performance parameters is proposed. In the proposed design the flipped voltage follower cell uses a MOS transistor in its feedback path, due to which the output impedance gets scaled down, which when applied for current mirror realization shows very low input resistance of about 48 ohms. The other improvement achieved is in terms of output resistance, for which the cascode approach has been utilized. The output resistance achieved is 3G ohms. The proposed current mirror operates with minimal error till 1 mA and exhibits very less input compliance voltage. The –3 dB bandwidth is about 890 MHz. The process corner, temperature analysis and Monte Carlo runs for the proposed design are also shown. The complete analysis is done using Spice on 0.18-um technology at a supply voltage of ± 0.5 V. [ABSTRACT FROM AUTHOR]