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Ni(Pt) films were silicided at nominally 400 °C. Electrostatic discharging (ESD) failure of devices occurred, which prompted root cause investigation. The silicide stack on the wafer was Ni(Pt)/Ni2Si(/Si). Flakes of SiO2 emerged on the wafer after the metal etch. With a higher silicidation temperature of 570 °C, the extent of the silicidation was greater. The stack on the wafer became Ni-oxide/Si-oxide/(NiPtx)Si/NiSi(/Si). The flaking issue was resolved and the desired etch selectivity achieved. It is the decomposition of Ni2Si that led to the bi-layer structure of NiSi, and the minimization of free energy that drove the out-diffusion of Ni and Si from the NiSi to form the surface oxides. Ni-oxide formed on Si-oxide because Si-oxide is thermodynamically more stable than Ni-oxide. The two layers of oxides and the density of bond energy of (NiPtx)Si being higher than that of Ni2Si made the stack more resistant to the metal etch and resulted in the desired etch selectivity. No reliability failure was observed after the flaking issue was addressed.

Ni(5 at.%Pt ) films were silicided at a temperature below 400 °C and at 550 °C. The two silicidation temperatures had produced different responses to the subsequent metal etch. Catastrophic removal of the silicide was seen with the low silicidation temperature, while the desired etch selectivity was achieved with the high silicidation temperature. The surface microstructures developed were characterized with TEM and Auger depth profiling. The data correlate with both silicidation temperatures and ultimately the difference in the response to the metal etch. With the high silicidation temperature, there existed a thin Si-oxide film that was close to the surface and embedded with particles which contain metals. This thin film is expected to contribute significantly to the desired etch selectivity. The formation of this layer is interpreted thermodynamically.

This paper demonstrates a method of analysis to determine a minimum achievable overlay design rule, for an existing stepper tool set in a high volume manufacturing fab. Overlay parameters and Critical Dimensions are considered in an overlay budget applying a modified algorithm to the evaluation of reticle errors, tool performance, and design rule analysis. The modified algorithm is used to determine the capability of an installed tool set of high NA steppers to meet the aggressive overlay requirements for advanced BiCMOS device performance. Design rule boundaries and tool set capability are thoroughly investigated. Experimental results from lithographic tests are used in a modified algorithm to determine the capability of running with current design rules or requiring a change for manufacturability. The impact of writing reticles to tighter specifications for both Critical Dimensions and pattern placement are considered. This study provides a method for chip designers and process engineers to determine the lithographic capability of an installed tool set where a part will eventually be fabricated. The results demonstrate that design rules demand optimum tool performance for overlay and CD control as well as provide a tool for the evaluation of continuous improvement.