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Object detection in video streams is often realized with Deep Neural Networks (DNNs), which require fetching, to the computing unit where they are executed, large volumes of weights to process each image of the video. In general, those weights largely exceed the capacity of on-chip cache memories in many applications (e.g., object detection in autonomous cars), and hence, pose high memory bandwidth requirements and induce a high energy consumption to fetch those many weights for each image. Solutions such as weight clustering to reduce the bits required to encode each weight, along with lower precision arithmetic to reduce the energy consumption of the accelerator running DNNs, are well-known solutions. However, they are often evaluated in small-scale setups that are not fully representative of the target applications, hence, limiting the value of the conclusions obtained. This paper covers this gap by evaluating the combined use of weight clustering and reduced precision arithmetic, for both floating point (FP) and integer arithmetic, at-scale with the You Only Look Once v3 (YOLOv3) camera-based object detector, used in a wide variety of industrial applications, including autonomous driving cars and trains. Our assessment shows that accuracy results degrade slowly as fewer bits are used for the (clustered) weights, but instead, bandwidth requirements and its associated power consumption decrease rapidly. When combining weight clustering with reduced precision arithmetic in the accelerator performing inference, both bandwidth requirements and energy consumption are reduced to 20-30% of those of the original YOLOv3 FP 32-bit implementation. Overall, our analysis shows that techniques such as weight clustering and reduced precision arithmetic provide large energy and bandwidth gains for real-life AI-based applications used for camera-based object detection, and provides guidance on the effectiveness of each technique., This work is part of the project REBECCA, funded by MICIU/AEI/10.13039/501100011033 and the European Union NextGenerationEU/PRTR under grant PCI2022-134984-2, and the European Union’s Horizon Europe Programme Chips Joint Undertaking (JU) under grant agreement No 101097224. This work has also been partially supported by the Spanish Ministry of Science and Innovation under grant PID2019-107255GBC21/AEI/10.13039/501100011033., Peer Reviewed, Postprint (author's final draft)

The accuracy of camera-based object detection (CBOD) built upon deep learning is often evaluated against the real objects in frames only. However, such simplistic evaluation ignores the fact that many unimportant objects are small, distant, or background, and hence, their misdetections have less impact than those for closer, larger, and foreground objects in domains such as autonomous driving. Moreover, sporadic misdetections are irrelevant since confidence on detections is typically averaged across consecutive frames, and detection devices (e.g. cameras, LiDARs) are often redundant, thus providing fault tolerance. This paper exploits such intrinsic fault tolerance of the CBOD process, and assesses in an automotive case study to what extent CBOD can tolerate approximation coming from multiple sources such as lower precision arithmetic, approximate arithmetic units, and even random faults due to, for instance, low voltage operation. We show that the accuracy impact of those sources of approximation is within 1% of the baseline even when considering the three approximate domains simultaneously, and hence, multiple sources of approximation can be exploited to build highly efficient accelerators for CBOD in cars., This work is partially funded by the DRAC project, which is co-financed by the European Union Regional Development Fund within the framework of the ERDF Operational Program of Catalonia 2014–2020 with a grant of 50% of total cost eligible. This work has also been partially supported by the Spanish Ministry of Science and Innovation under grant PID2019-107255GB., Peer Reviewed, Postprint (author's final draft)

Systolic array architectures have recently emerged as successful accelerators for deep convolutional neural network (CNN) inference. Such architectures can be used to efficiently execute general matrix–matrix multiplications (GeMMs), but computing convolutions with this primitive involves transforming the 3-D input tensor into an equivalent matrix, which can lead to an inflation of the input data, increasing the off-chip memory traffic which is critical for energy efficiency. In this work, we propose a GeMM-based systolic array accelerator that uses a novel data feeder architecture to perform on-chip, on-the-fly convolution lowering (also known as im2col), supporting arbitrary tensor and kernel sizes as well as strided and dilated (or atrous) convolutions. By using our data feeder, we reduce memory transactions and required bandwidth on state-of-the-art CNNs by a factor of two, while only adding an area and power overhead of 4% and 7%, respectively. Application specific integrated circuit (ASIC) implementation of our accelerator in 22-nm technology fits in less than 1.1 mm 2 and reaches an energy efficiency of 1.10 TFLOP/sW with 16-bit floating-point arithmetic., This work was supported in part by the MCIN/AEI/10.13039/501100011033 under Project PCI2020-134984-2, in part by the European Union NextGenerationEU/PRTR, in part by the European Union’s Horizon Europe Program under Project Key Digital Technologies (KDT) Joint Undertaking (JU) under Grant 101097224, and in part by the Spanish Ministry of Science and Innovation through MCIN/AEI/10.13039/501100011033 under Grant PID2019-107255GB-C21., Peer Reviewed, Postprint (author's final draft)

Deep neural networks are the dominant models for perception tasks in the automotive domain, but their high computational complexity makes it difficult to execute them in real time with an acceptable power consumption on general-purpose devices. For this reason, the design of custom ASIC devices for real-time energy-efficient neural network deployment is a hot topic in academia and industry. Low-precision integer arithmetic and approximate computing are two popular optimizations often contemplated for saving hardware resources and power consumption. In this work, we evaluate two approximate computing circuits using different integer precisions in order to study the trade-offs that these techniques offer in terms of energy efficiency and degradation of the neural network outputs. In particular, we apply the approximations to the YOLOv3 object detection network, a popular model for critical applications in the automotive domain. By combining approximate arithmetic circuits with low precision we are able to reduce the power consumption of a MAD unit by over 50% compared to using only quantization., Peer Reviewed, Postprint (author's final draft)

Automotive applications with safety requirements must adhere to specific regulations such as ISO 26262, which imposes the use of diverse redundancy for the highest integrity levels (i.e., ASIL D). While this has been often achieved by means of Dual-Core LockStep (DCLS) for microcontrollers, it remains an open challenge how to realize diverse redundancy efficiently, i.e., without full duplication and preserving performance, for DNN-based safety-related tasks, such as object detection, needing accelerators for performance reasons.This paper proposes an architecture where the accelerator performing DNN inference is replicated, as in the case of DCLS for cores, but using a cheaper implementation for the replica. In particular, we build on the stochastic nature of DNN-based object detection to realize two redundant accelerators where the secondary accelerator uses smartly chosen lower precision arithmetic (e.g., dropping some bits of the original data) so that it provides diverse redundancy, it can keep the performance of the primary accelerator, does not require as much cost as full- precision replication, and can build on the very same data stream from memory used by the primary accelerator. With a simple heuristic, we show that such a diverse redundancy scheme is able to cope with faults restricting false positives and negatives to a few relatively small objects., The research leading to these results has received funding from the European Union’s Horizon Europe Programme under the SAFEXPLAIN Project (www.safexplain.eu), grant agreement num. 101069595. This work has also been partially supported by the Spanish Ministry of Science and Innovation under grant PID2019-107255GBC21/AEI/10.13039/501100011033., Peer Reviewed, Postprint (author's final draft)

Actualment els multiplicadors són una de les unitats funcionals que requereixen més consum d'energia degut al gran nombre de portes lògiques que contenen. Aprofitant el fet que diverses aplicacions poden tolerar un cert error en el resultat del càlcul de les multiplicacions, principalment aplicacions relacionades amb els sentits de l'ésser humà ja que els nostres sentits no són perfectes, podem implementar multiplicadors aproximats que realitzen el càlcul de la multiplicació de manera aproximada i permeten reduir el consum d'energia, mantenint un error relatiu petit en el resultat de l'operació. En aquest projecte s'estudien diverses implementacions de multiplicadors aproximats de 8, 16 i 32 bits i també s'ha estudiat l'efecte de combinar multiplicadors aproximats en una mateixa implementació., Currently multipliers are one of the functional units that consume more energy due to the large number of logic gates used. Taking advantage of the fact that some applications tolerate a small error on the result of the multiplications, mainly applications related to the human senses since our senses are not perfect, we can implement approximate multipliers that calculate the result of the multiplications approximately and, hence, reduce the energy needed while maintaining a small relative error in the result of the operation. In this project, we study different approximate multiplier implementations of 8, 16 and 32 bits and we also study the effect of combining different implementations of approximate multipliers in one implementation.