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The effects of 1 MeV electron irradiation upon the performance of two phase, polysilicon aluminum gate CCDs are reported. Both n- and p-surface channel and n-buried channel devices are investigated using 64- and 128-stage line arrays. Characteristics measured as a function of radiation dose include: Transfer inefficiency, threshold voltage, field effect mobility, interface state density, full well signal level and dark current. Surface channel devices are found to degrade considerably at less than 10 to the 5th power rads (Si) due to the large increase in fast interface state density caused by radiation. Buried channel devices maintain efficient operation to the highest dose levels used.

The performance of experimental two phase, charge-coupled shift registers constructed using polysilicon gates overlapped by aluminum gates was studied. Shift registers with 64, 128, and 500 stages were built and operated. Devices were operated at the maximum clock frequency of 20 MHz. Loss per transfer of less than .0001 was demonstrated for fat zero operation. The effect upon transfer efficiency of various structural and materials parameters was investigated including substrate orientation, resistivity, and conductivity type; channel width and channel length; and method of channel confinement. Operation of the devices with and without fat zero was studied as well as operation in the complete charge transfer mode and the bias charge, or bucket brigade mode.

A charge-transfer efficiency of 99.99% per stage was achieved in the fat-zero mode of operation of 64- and 128-stage two-phase charge-coupled shift registers at 1.0-MHz clock frequency. The experimental two-phase charge-coupled shift registers were constructed in the form of polysilicon gates overlapped by aluminum gates. The unidirectional signal flow was accomplished by using n-type substrates with 0.5 to 1.0 ohm-cm resistivity in conjunction with a channel oxide thickness of 1000 A for the polysilicon gates and 3000 A for the aluminum gates. The operation of the tested shift registers with fat zero is in good agreement with the free-charge transfer characteristics expected for the tested structures. The charge-transfer losses observed when operating the experimental shift registers without the fat zero are attributed to fast interface state trapping. The analytical part of the report contains a review backed up by an extensive appendix of the free-charge transfer characteristics of CCD's in terms of thermal diffusion, self-induced drift, and fringing field drift. Also, a model was developed for the charge-transfer losses resulting from charge trapping by fast interface states. The proposed model was verified by the operation of the experimental two-phase charge-coupled shift registers.

A simple model is presented that makes it possible to predict signal losses in charge-coupled devices due to fast-interface-state trapping. Presented experimental losses in a twelve-bit two-phase charge-coupled device with overlapping Si and Al gates are shown to agree well with the prediction of the model.