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This paper exploits the possibility of monitoring the floating-gate (FG) charge of state-of-the-art NAND Flash arrays with a single-electron resolution to investigate in detail the program operation and some previously inaccessible technological parameters. In particular, the analysis leads to the assessment of the statistical distribution of the FG to control-gate capacitance and of the leakage current from the FG through the intergate dielectric during the programming pulses. Results highlight that resolving the FG charge at the single-electron level opens new prospects for the investigation of the operation and the parameters of NAND Flash arrays.

This letter investigates the major differences between planar (2-D) and vertical-channel (3-D) NAND Flash memory arrays in terms of their temperature dependences. Attention is focused on three relevant parameters for memory array operation, namely, cell threshold-voltage, string saturation current, and width of the random telegraph noise distribution. Results highlight that the transition from2-D to 3-D arrays introduced non-negligible changes in the temperature behavior of these parameters, whose origin is traced back to the different channel material of the technologies, i.e., monocrystalline versus polycrystalline silicon.

This letter highlights a random telegraph noise-induced sensitivity of the data retention threshold-voltage transient of nand Flash memory cells to their position in the programmed array distribution. This sensitivity appears with a reduction of the threshold-voltage loss of the cells in the lower part of the programmed distribution of the memory array and an increase of that of the cells in the upper part of the distribution. The experimental evidence is explained considering the impact of random telegraph noise on the programmed array distribution in the stretch of time in-between the program-and-verify operation and the first read operation used as reference for data retention assessment.

This letter provides the first direct experimental detection of single-electron charging of the floating gate of a mainstream Flash memory cell. The detection is shown to be easily achievable through conventional and very simple measurement techniques on state-of-the-art technologies. Results represent a milestone for the investigation of the physics of Flash memory operation, opening the possibility for direct analyses of the piling up of single electrons in the floating gate during cell programming.

In this work, we present clear experimental results pointing to a new microscopic picture for cycling-induced charge trapping/detrapping in Flash memories. In particular, the evidence gathered from experiments designed to investigate the dependence of charge detrapping on cell threshold-voltage reveals that the simple and widely used model based only on carrier exchange between oxide defects and substrate is not enough to explain the main features of the phenomenon. We then propose a new microscopic description of the detrapping phenomenology, including structural relaxation of oxide defects as a limiting step enabling carrier exchange. This new microscopic picture for the oxide defects is, finally, implemented in a statistical model able to reproduce the charge trapping/detrapping dynamics and the consequent threshold-voltage instabilities along the memory array lifetime.

This paper presents a detailed investigation of the impact of cycling time and temperature on the threshold-voltage instability arising from damage recovery during data retention on nanoscale nand Flash. Statistical results from the programmed state show that instabilities result, on average, in a threshold-voltage loss, which increases logarithmically with the time elapsed since the end of cycling. The slope of the logarithmic behavior strongly depends on the electric field during data retention, the cycling dose, and the probability level at which the shift of the array cumulative distribution is monitored. Increasing the cycling time and temperature corresponds, instead, to an equivalent delay of the instant at which the first read operation on the array is performed. The delay is studied for a large variety of cycling and retention conditions, extracting the parameters required for a universal damage-recovery metric for nand.

This work aims at providing an accurate and flexible tool to simulate the most advanced placement algorithms for state-of-the-art NAND Flash devices. A model for incremental step pulse programming is discussed and experimentally validated, showing its capability to describe the dependence on the program pulse duration/amplitude and to correctly reproduce the proximity effect and the selective slow program convergence behavior, when a bit line/channel bias is applied. Finally, when the entire memory array is simulated in a Monte Carlo fashion, the placement of our decananometer 3bit/cell device can be accurately reproduced, including the behavior of the advanced programming features.

We conduct a thorough investigation of random telegraph noise (RTN) dependence on program/erase and read/bake conditions in state-of-the-art 1X and 2X Flash NAND technologies. We demonstrate that RTN depends only on the cycle number and not on the program level or cycling pattern. Moreover, if the cumulative distribution of RTN is considered, a negligible temperature dependence appears, in apparent contrast with thermal activation of single-trap time constants. RTN appears also to be independent of the read and bake temperature, although a slight asymmetry in the distribution tails is induced by charge detrapping. A Monte Carlo model is also presented to account for the experimental observations.

Introduction: Random telegraph noise (RTN) during read and charge detrapping during data retention cause time dependent threshold voltage (VT) fluctuations in NAND flash memories [1-9]. This paper reviews and discusses the physics of these phenomena and the impact on NAND array reliability based on characteristics of aggressively scaled 2D planar NAND cells [10][11]. The discussion is further extended to 3D NAND.

We present the first single-electron analysis of the program operation of NAND Flash arrays. The analysis leads, first of all, to a direct extraction not only of the average value but also of the statistical spread of the control-gate to floating-gate cell capacitance (Cpp). This allows, then, to assess the impact of Cpp variability, electron injection statistics and read noise on the distribution of the threshold-voltage shift coming from a programming pulse applied to the array cells. Finally, the electron leakage through the inter-gate dielectric along program is easily and directly quantified under real operating conditions.

We present a semi-analytical model for the description of charge trapping and detrapping phenomena occurring during cycling and idle periods in NAND Flash memories. The model is based on a statistical distribution of detrapping time constants that is affected by the composition of cycles and idle periods and accounts for charge discreteness, statistical charge capture and emission and statistical distribution of the threshold-voltage shift due to single detrapping events. The model can reproduce the experimental data under different conditions and allows to develop and monitor accelerated schemes able to mimic realistic on-field usage of the memory device.

Starting from the theoretical background on the detrapping process in nanoscale Flash memories given in Part I of this paper [1], we address here the effect of idle periods, temperature, and program/erase cycles on the spectral distribution of detrapping events and, in turn, on threshold-voltage instabilities appearing during a data retention time stretch. In so doing, we come to a comprehensive model able to deal with threshold-voltage instabilities from whatever on-field usage or testing scheme of the memory array, carefully accounting for both charge trapping and detrapping, and reproducing distributed-cycling effects. The model represents a valuable tool for the predictive reliability analysis of Flash technologies and for the development of accelerated experimental schemes for the assessment of post-cycling thereshold-voltage instabilities coming from charge detrapping.

This work is focused on the accelerated testing of Flash memory reliability, taking our 45 nm NOR technology as a case study to highlight some major issues that may affect the investigation of modern nanoscale devices. In particular, results will be shown on cycling-induced threshold-voltage instabilities coming from charge trapping/detrapping in the cell tunnel oxide during post-cycling data retention or bake experiments, whose characterization relies on the possibility to reduce the experimental time by an increase of the test temperature according to an Arrhenius law via an activation energy EA. These accelerated characterization schemes come from a detailed physical understanding and modeling of the damage creation/recovery dynamics and rely on the careful evaluation of EA. As shown in the case of the investigated NOR technology, this often does not represent a trivial task, due to the large number of spurious effects affecting the threshold voltage of nanoscale memory cells.

We report the first experimental evidence of discrete threshold-voltage transients on high-density NAND Flash arrays during post-cycling data retention. Proper choice of experimental conditions eliminates the impact of averaging effects and disturbs on the transients, enabling clear detection of single charge emission events from/to the tunnel oxide of sub-30nm NAND Flash cells. A stochastic model for the discrete emission process was developed from experimental data, demonstrating that number fluctuation of charges trapped in the tunnel oxide and the statistical nature of their emission dynamics strongly affect the post-cycling data retention performance of the arrays. These results pave the way for further analyses of NAND Flash reliability, where the behavior of single electrons and defects can be monitored and facilitate detailed assessments of the fundamental scaling challenges arising from the discrete nature of charge trapping/detrapping.

This paper shows that the reliability characterization of nanoscale Flash memories requires an accurate control of the adopted experimental tests, preventing spurious issues to emerge and alter the basic conclusions on the investigated reliability constraints. To this aim, the paper reports a case study on a 45-nm NOR technology, where the experimental investigation of the activation energy for damage recovery during post-cycling bakes and of distributed-cycling effects is substantially affected by parasitic threshold-voltage (VT) drifts, activated by the repeated acquisition of the whole array VT map during the experiment. Only when this spurious effect is taken into account, the typical 1.1-eV activation energy for damage recovery and the effectiveness of the conventional distributed-cycling schemes are correctly demonstrated on the investigated technology.

This paper investigates the validity of distributed-cycling schemes on scaled Flash memory technologies. These schemes rely on the possibility to emulate on-field device operation by increasing the cycling temperature according to an Arrhenius law, but the assessment of the activation energy that has to be used on scaled technologies requires a careful control of the experimental tests, preventing spurious second-order effects to emerge. In particular, long gate-stresses required to gather the array threshold voltage (V T ) map are shown to give rise to parasitic V T -drifts, which add to the V T -loss coming from damage recovery during post-cycling bake. When the superposition of the two phenomena is taken into account, the effectiveness of the conventional qualification schemes relying on a 1.1 eV activation energy is fully confirmed at the 45 nm NOR node.

This paper presents a detailed compact-modeling investigation of the string current in decananometer nand Flash arrays. This investigation allows, first of all, to highlight the role of velocity saturation, low-field mobility, and drain-induced barrier lowering on the string current versus read voltage characteristics. Results are validated on a 41-nm technology for different positions of the selected cell along the nand string, different pass voltages, and different array background patterns. The effect of cycling on the string current is then investigated by means of postcycling bake experiments, showing that the impact of charge trapping/detrapping and interface state generation/annealing varies as a function of the read current level. Compact-modeling results display that, at low read currents, charge trapping/detrapping represents the main damage mechanism for the cells, while interface states come into play for read currents close to the string saturation level via mobility degradation.

Cycling-induced threshold-voltage instabilities in NAND Flash memory arrays are investigated via compact modeling of the NAND string. Calibration against experimental data allows the extraction of the model parameters and of their dependence on cycling dose and post-cycling bake time. Results are used to study the impact of charge trapping/detrapping in the tunnel oxide and interface state generation/annealing on the damage creation and recovery dynamics. It is shown that the former mechanism represents the main responsible for threshold-voltage instabilities, while interface states come into play at high read currents, accelerating the threshold-voltage transients and lowering their activation energy during bakes below 1.1eV.

This paper presents a detailed investigation of the performance of a double-verify algorithm for accurate programming of deca-nanometer NAND Flash memories. In order to minimize the programmed threshold-voltage distribution width in presence of discrete and statistical electron injection, a weakened programming step is applied to cells if their threshold voltage falls between a low- and a high-program-verify level during incremental step pulse programming. Clear improvements are shown with respect to the single-verify case, with minimal burdens on programming time and complexity.

This letter investigates the impact of control-gate (CG) and floating-gate (FG) doping and geometry on the electron-injection spread (EIS) of nanoscale NAND Flash memories. Doping of CG polysilicon rules the reduction of the CG-to-FG capacitance when moving from the read to the program conditions, as a result of polysilicon depletion. The capacitance reduction is shown, however, to be nearly negligible for the EIS resulting from incremental step pulse programming, which, for the commonly adopted voltage steps, is mainly determined by the capacitance value in read conditions. Finally, the scaling trend of the CG-to-FG capacitance and of the EIS is addressed, discussing the evolution of the FG polysilicon in terms of geometry and dimensions.

This paper presents a detailed experimental investigation of the cycling-induced threshold voltage instability of deca-nanometer NAND Flash arrays, focusing on its dependence on cycling time and temperature. When the array is brought to a programmed state after cycling, instability mainly shows up as a negative shift of its threshold voltage cumulative distribution, increasing with time and resulting from partial recovery of cell damage created in the previous cycling period. The threshold voltage loss displays a strong dependence not only on the tunnel oxide electric field during retention, but also on the cycling conditions. In particular, performing cycling over a longer time interval or at higher temperatures delays the threshold voltage transients on the logarithmic time axis. The delay factor is studied as a function of the cycling duration and temperature on 60 and 41 nm technologies, extracting the parameter values required for a universal damage-recovery metric for NAND.

This letter presents a comparison of two different variability sources for data retention of nanoscale NAND Flash memories: the neutral threshold-voltage spread and the electron-emission statistics from the floating gate. Referring to fresh cells programmed to the same threshold-voltage level, the effect of the previous dispersion contributions on the data retention transients of a memory array is evaluated. Both effects are shown to result into a broadening of the array threshold-voltage distribution with time, but a quantitative assessment clearly shows that the neutral threshold-voltage spread dominates over the electron-emission spread, revealing that cell-to-cell parameter variations represent the major source of variability for data retention in nanoscale NAND Flash memories.