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A low-power ultrasonic communication system conceived for cargo container monitoring is presented. Two piezoelectric transducers operating at 40 kHz are used for generating and acquiring an ultrasonic signal through the metallic wall, thus establishing a non-invasive inside-outside communication that preserves the container integrity. Both transducers are fixed by means of a novel magnetic case designed for optimizing data transmission. The acoustic and electrical characteristics of the ultrasonic channel are analyzed. An experimental measurement setup based on FPGA has been implemented for comparing some basic modulation and detection schemes in terms of Bit Error Rate (BER), also considering their robustness against undesired mechanical and electromagnetic perturbations. On this basis, a compact digital DBPSK modulator using a square carrier signal is proposed. Frequency and amplitude tracking algorithms are designed for optimizing the quality and robustness of the data transmission. Finally, a low-power low-rate (up to few kbps) architecture based on the previous elements is presented. All the proposed contributions are experimentally validated. This work was supported in part by Spanish Agencia Estatal de Investigación and Fondo Europeo de Desarrollo Regional under Grant TEC2016-80396-C2-1-R, and in part by the Obra Social La Caixa, Fundación Caja Navarra (Convocatoria 2018 de Captación de Talento).

This paper proposes a novel, tunable AC coupled capacitive feedback amplifier, exhibiting an ultra-low high pass corner frequency. This is accomplished by actively boosting the output resistive value of a MOS transistor in weak inversion. The circuit is based on a more general architecture, recently proposed by the authors, and is analyzed in terms of its capability to achieve ultra-low frequency operation, its DC performance, and noise. The proposed technique is demonstrated via measurement results from a fabricated test chip prototype using a standard 0.18 µm CMOS technology. The proposed amplifier provides a tunable high pass corner frequency from 20 mHz to 475 mHz, consuming 4.71 μW and a total area of 0.069 mm2. Grant PID2019-107258RB-C32 (AEI/FEDER), Ministry of Universities (grant BES-2017-080418) and Public University of Navarra. Open Access funding provided by Public University of Navarra

A novel architecture for an AC (i.e. high-pass) amplifier is proposed allowing a drastic reduction of the cutoff frequency to the sub-Hertz range. It builds upon the classic AC configuration with a high gain amplifier and a parallel RC circuit in the feedback loop, by increasing the feedback resistance through bootstrapping. Resistance multiplying factors higher than four orders of magnitude are easily achievable. The basic principle can be applied to several practical implementations, though in this letter it is demonstrate with measurement results of an op-amp based discrete implementation. This work was financially supported by the following grants from the Spanish Research Agency: TEC2016-80396-C2-1-R and PID2019-107258RB-C32 (AEI/FEDER). M.Martincorena Arraiza was funded by the Ministry of Universities under grant BES-2017-080418.

A novel current-mode CMOS RMS-to-DC converter using translinear techniques is introduced. It is based on a Squarer/Divider cell that is implemented using an electronically simulated loop with a novel biasing scheme that allows its operation in two quadrants. The cell is designed using a differential input current and a small signal first order filter to implement the voltage averaging, leading to a compact solution that can be used with low voltage supplies. The converter has been fabricated in a standard 130 nm CMOS process, and measurement results are provided to demonstrate the feasibility of the system.

An enhanced single-stage folded cascode operational transconductance amplifier able to drive large capacitive loads is presented. Circuits that adaptively bias the input differential pair and the current folding stage are employed, which provide class AB operation with dynamic current boosting and increased gain-bandwidth (GBW) product. Measurement results of a test chip prototype fabricated in a 0.5- $\mu$ m CMOS process show an increase in slew rate and GBW by a factor of 30 and 15, respectively, versus the class A version using the same supply voltage and bias currents. Overhead in other performance metrics is small.