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Abstract Dynamic random-access memory (DRAM) has been scaled down to meet high-density, high-speed, and low-power memory requirements. However, conventional DRAM has limitations in achieving memory reliability, especially sufficient capacitance to distinguish memory states. While there have been attempts to enhance capacitor technology, these solutions increase manufacturing cost and complexity. Additionally, Silicon-based capacitorless memories have been reported, but they still suffer from serious difficulties regarding reliability and power consumption. Here, we propose a novel Schottky barrier memory (SBRAM), which is free of the complex capacitor structure and features a heterojunction based on bandgap engineering. SBRAM can be configured as vertical cross-point arrays, which enables high-density integration with a 4F2 footprint. In particular, the Schottky junction significantly reduces the reverse leakage current, preventing sneak current paths that cause leakage currents and readout errors during array operation. Moreover, the heterojunction physically divides the storage region into two regions, resulting in three distinct resistive states and inducing a gradual current slope to ensure sufficient holding margin. These states are determined by the holding voltage (V hold) applied to the programmed device. When the V hold is 1.1 V, the programmed state can be maintained with an exceptionally low current of 35.7 fA without a refresh operation.

Dynamic random-access memory (DRAM) has been scaled down to meet high-density, high-speed, and low-power memory requirements. However, conventional DRAM has limitations in achieving memory reliability, especially sufficient capacitance to distinguish memory states. While there have been attempts to enhance capacitor technology, these solutions increase manufacturing cost and complexity. Additionally, Silicon-based capacitorless memories have been reported, but they still suffer from serious difficulties regarding reliability and power consumption. Here, we propose a novel Schottky barrier memory (SBRAM), which is free of the complex capacitor structure and features a heterojunction based on bandgap engineering. SBRAM can be configured as vertical cross-point arrays, which enables high-density integration with a 4F2 footprint. In particular, the Schottky junction significantly reduces the reverse leakage current, preventing sneak current paths that cause leakage currents and readout errors during array operation. Moreover, the heterojunction physically divides the storage region into two regions, resulting in three distinct resistive states and inducing a gradual current slope to ensure sufficient holding margin. These states are determined by the holding voltage (Vhold) applied to the programmed device. When the Vhold is 1.1 V, the programmed state can be maintained with an exceptionally low current of 35.7 fA without a refresh operation. [ABSTRACT FROM AUTHOR]

Capacitorless two‐transistor (2T0C) dynamic random‐access memory (DRAM) cells comprising oxide thin‐film transistors (TFTs) show potential as low‐power and high‐density DRAM cells; however, the multiply–accumulate (MAC) operation using these cells is not yet realized. In this study, 2T0C DRAM cells comprising amorphous indium–tin–gallium–zinc oxide TFTs are fabricated for MAC operations. In a 2T0C DRAM cell, one transistor acts as a write transistor and the other as a read transistor, whose gate capacitance corresponds to the data storage capacitance. The cells have a long retention time of 1000 s, which is 104 times longer than that of conventional DRAM cells, owing to the extremely low leakage current of the TFTs (1.11 × 10−18 A µm−1). These cells satisfy the original condition for synaptic devices, in which a proportional relationship exists between the input and output. The MAC operation is performed using two cells. This study demonstrates the usefulness of oxide TFTs in artificial neural networks. [ABSTRACT FROM AUTHOR]

This work showcases the implementation of 16 Boolean logic functions through a double-gate (DG) fully depleted (FD) Silicon-on-Insulator (SOI) Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET). The DG-FD-SOI device with an independent gate operation highlights that Boolean logic functions can be implemented in two steps (Program and Read), and Boolean logic output “High” (“1”) and “Low” (“0”) depends on the floating body effect. The Program (Step 1) operation is based on band-to-band tunneling and forward bias mechanisms, while the Read (Step 2) operation is based on drift and impact ionization mechanism. The program and read operations for logic-in-memory computing are performed in ~10 ns and consume low energy ( $\sim 4.04\times 10 ^{-14}$ J) during the read operation. The results also show that the device with optimized device dimensions, biasing, and timing scheme achieves a drain current ratio of $\sim 10^{5}$ . These results reveal that DG-FD-SOI-based MOSFET for logic-in-memory computing is a compelling alternative to the limitations of von Neumann architectures, offering significant speed and energy efficiency advantages.

TCAD simulation using Silvaco software has shown that the 3G_DFM, which has SG1 (Select Gate 1), PL (Plate Line Gate), and SG2 (Select Gate 2) between SL (Source Line) and BL (Bit Line), has a long retention time of 100ms at 85 °C, and a robust disturbance shield which is a thousand times BL stress. The two select gates SG1 and SG2 protect the recombination of holes in the FB (Floating Body) at the SL and BL pn-junctions, and shield the BL stress arising during other page operations, which leads to the GIDL (Gate Induced Drain Leakage) current.

• Capacitorless DRAM Performance according to the Junctionless GAA Structure Parameter and Stacked GAA. • Channel Thickness has a significant impact on Sensing Margin. • Secure 100 ms improved Retention Time at 6 nm Channel Thickness at Single GAA Structure. • The Contrast of Sensing Margin and Retention Time in Staked Nanosheet Structure. The characteristic comparison of the capacitor-less DRAMs in the structural form variation is investigated. Based on the simulation results of the three basic structures, such as circular, square, and rectangular nanosheets, the gate length (L g), channel thickness (T si), and width of the nanosheet (W si) are considered as the main factors in design and the characteristic variations are verified according to the junctionless (JL) gate-all-around (GAA) geometry factors. The channel thickness is a major factor that has a major influence on the sensing margin and the retention time, which are important characteristics of DRAM. The thinner the thickness, the more deteriorated the sensing margin is confirmed. Retention time is due to the influence of the electric field distribution of the JL GAA structure, resulting in differences in structure. Finally, the rectangular type nanosheet is implemented in the stacked structure. As the number of stacks increases, the effective channel width increases compared to the layout footprint. In addition, by stacking vertically, the area where holes can be stored increases. Therefore, the sensing margin tends to increase as the number of stacks increases. However, the difference in diffusion due to the difference in the initially stored hole density, the retention time deteriorates as the number of stacks increases. [ABSTRACT FROM AUTHOR]

This paper proposes a Dynamic Flash Memory (DFM) (Sakui and Harada, 2020; 2021 [1,2]) with double storage gates and one select gate based on FinFET and Surrounding Gate Transistor (SGT) (Takato et al., 1988 [3]) architectures. Like DRAM (Dennard, 1967 [4]), refresh is required, but fast block refresh improves the duty ratio. Analogous to Flash (Masuoka, 1981 [5]), three basic operations of “0” Erase, “1” Program, and Read are necessary, but the ability to carry out Read-While-Erase (RWE), and Program-While-Erase (PWE) operations in the background results in a faster system.

In this letter, a Si-based two-terminal (2-T) thyristor random-access memory (TRAM) device is designed and characterized, and its operation window and power consumption are closely investigated by technology computer-aided design (TCAD) simulation. The properly scaled 2-T TRAM device has higher reliability since it can rule out impact ionization. Write time ( T\text {write} ) and erase time ( T\text {erase} ) reach below 10 ns and zero energy is consumed to hold state achieving high competitiveness with the existing dynamic random-access memory (DRAM). The state current ratio reaches higher than 105. Also, V\text {write} and erase voltage ( V\text {erase} ) of the 2-T TRAM appear to be below 2 and −1.2 V, respectively, in the permissible operation window, with less energy consumption compared with the conventional ones. The 2-T TRAM is a strong candidate for capacitorless DRAM technology. [ABSTRACT FROM PUBLISHER]

A2RAM prototype devices have been demonstrated in both SOI and bulk technologies. The fabrication process has successfully achieved the characteristic retrograde doping profile of the channel which allows the coexistence of electrons and holes in the same body while maintaining low-voltage single-gate operation. The different prototypes have been electrically characterized, all of them exhibiting memory effect. The SOI samples present the best performance, showing very attractive current margin between states, competitive retention time, reasonable variability, immunity to disturbance events and no endurance issues even in the short-channel devices fabricated in the most advanced 22 nm process. [ABSTRACT FROM AUTHOR]

Abstract: We demonstrate a new fully depleted (FD) double-gate (DG) MSDRAM cell, which features SONOS type storage node at the back-gate (control-gate). This single-transistor cell, based on the meta-stable dip (MSD) hysteresis effect, can also be operated in non-volatile memory (NVM) mode. The NVM functionality is achieved by Fowler–Nordheim tunneling hole injection into the nitride storage node; the injected holes induce a permanent inversion layer in silicon body. The proposed device shows a large current ratio between ‘1’ and ‘0’ states (∼103) and a wide memory window (∼3V). The effect of the NVM functionality on the MSD hysteresis was investigated and combined with the effect of the control-gate bias. The SONOS charging can be used for replacing the second gate (i.e. enabling single-gate MSDRAM) or for achieving ‘unified’ memory operation. [Copyright &y& Elsevier]

Abstract: A novel DRAM cell based on floating junction gate (FJG) concept is investigated for its extended applications. Compared to the two-transistor floating gate DRAM cell, the new memory cell investigated in the present work has a much simpler configuration with only one transistor. Besides, its write speed is improved by introducing an integrated gated-diode so that state “1” can be self-refreshable. In this paper, the device configuration, the DRAM application feasibility, the self-refreshing ability, and the non-destructive read are explored. In addition, extended applications of the DRAM cell using the FJG concept will be discussed. [Copyright &y& Elsevier]

We proposed for the first time a new double-gate 1T-DRAM cell to be applicable to sub-80-nm DRAM technology that has a silicon-oxide--nitride-oxide--silicon type storage node on the back gate (control gate) for nonvolatile memory (NVM) functionality. An NVM functionality is achieved by Fowler--Nordheim tunneling of electrons into the nitride storage node. Then, holes are accumulated on the back-channel, which makes 1T-DRAM operation in fully depleted silicon-on-insulator (SOI) MOSFETs possible and enhances retention characteristics. We investigated the effect of the NVM functionality on 1T-DRAM performance in nanoscale 1T-DRAM cells through device simulation and verified the effect in 0.6-µm devices fabricated on SOI wafers. [ABSTRACT FROM AUTHOR]

A novel initialization concept is demonstrated to improve the program efficiency of the 1T-DRAM mode of unified random access memory (URAM). The proposed method involves boosting the gate-induced drain leakage current for the generation of excess holes by pretrapping electrons to the nitride layer prior to the activation of 1T-DRAM mode. The proposed initialization concept doubles the current sensing window in 1T-DRAM operation. Due to the potential for soft erasing caused by hot-hole injections into electrons that are trapped in the nitride during the P/E cycling of 1T-DRAM, immunity against soft erasing is confirmed through a dc stress measurement as well. [ABSTRACT FROM AUTHOR]

A novel two-transistor (2T) floating-body cell (FBC) for embedded-DRAM applications is proposed and demonstrated via device/circuit simulations using a process/physics-based compact model, with numerical-simulation support. Significant advantages of the 2T cell, in which the charged/discharged body of one transistor (1T) drives the gate of the other, over the currently popular 1T-DRAM FBC are noted and explained. Furthermore, a modification of the basic 2T-FBC structure, which in essence results in a floating-body/gate cell (FBGC), is shown to yield dramatic reduction in power dissipation in addition to better signal margin, longer data retention, and higher memory density. Design and processing issues that need to be addressed for optimal performance and for sustained FBGC viability in nanoscale CMOS are discussed. [ABSTRACT FROM AUTHOR]

A twin-transistor random access memory (TTRAM) can provide high speed, low power and high density with CMOS compatible SOI process. However it is difficult to handle as the unified memory required for advanced SoC because it needs the simple control sensing operation for memory compiler, higher cell efficiency, and lower voltage operation for dynamic frequency and voltage control. Enhanced TTRAM (ET²RAM) applies the actively body-bias control technique to realize the low voltage array operation, and never require the negative voltage source. The ET2RAM can realize both 263 MHz at 0.8 V and 10.2 mW at 0.5 V random-cycle operation, higher cell efficiency, and process scalability. It also provides the simple control method suitable for the unified macro for system-level power management SoC with keeping the merits of TTRAM as CMOS compatibility. [ABSTRACT FROM AUTHOR]

This letter reports on the spike anneal temperature influence on the retention time of 1T-dynamic random access memory cells using a single silicon-on-insulator transistor on ultrathin buried oxide wafers. A 20 ^\circC temperature difference (from 1070 ^\circC to 1050 ^\circC ) in the peak process temperature during the spike anneal after the source/drain implantation caused an order of magnitude increment in the retention time. The lower temperature analyzed (1050 ^\circC ) increases the retention time up to 100 ms because of the lower drain electrical field and tunneling current. [ABSTRACT FROM AUTHOR]

A capacitorless DRAM cell, floating-body/gate cell (FBGC), is experimentally presented with planar partially depleted SOI CMOS technology. The specially designed gate/drain underlap and gate/source overlap of the first transistor enable long worst case retention time as well as the fast write speed. The operation power dissipation is dramatically reduced while maintaining high sense margin. In addition, FBGC demonstrates excellent endurance performance and nondestructive read operation. [ABSTRACT FROM PUBLISHER]

Variability in back-gated thin-body capacitorless DRAM cell performance is investigated via TCAD simulation. Sources of variability considered include variations in front gate oxide thickness, body thickness, buried oxide thickness, and gate-sidewall spacer width, as well as random dopant fluctuations. Bipolar junction transistor-based cell operation is most sensitive to variations in body thickness and buried oxide thickness. Retention time for an optimized 22 nm-node cell design is predicted to be reduced by approximately 63% due to process-induced variations. [ABSTRACT FROM AUTHOR]

A novel modification of our “2T” floating-body/gate DRAM cell is described and, via numerical simulations, shown to yield very long charge data retention times under worst-case conditions, as well as good memory performance (i.e., large signal margin and low operating power). Relatively low voltage operation is enabled, thereby implying good cell reliability as well. [ABSTRACT FROM AUTHOR]

For the first time, we propose and experimentally demonstrate a novel single-transistor (1T) DRAM: Capacitorless Single-Transistor Charge-Trap DRAM (1T CT DRAM). The memory operation is obtained by engineering the body of the transistor with CTs by creating intentional electron-trapping zones. This memory makes use of charge traps and uses the existence or absence of electrons in its body instead of holes that are conventionally used in 1T DRAMs whose operation depends on floating-body effects. The DRAM operation is experimentally demonstrated. [ABSTRACT FROM AUTHOR]

A BJT-based 1T-DRAM that utilizes a latch process is analyzed in an experimental assessment. The experimental study reveals that undesired activation of a parasitic BJT by a high leakage current inhibits aggressive scaling of a BJT-based 1T-DRAM. Given the importance of choosing proper operation biases, the drain voltage that triggers the latch process in the BJT-based 1T-DRAM should be reduced to avoid unwanted parasitic BJT activation. Hence, a heterogeneous source and drain is proposed to ensure the energy bandgap offset to silicon channel. A numerical evaluation confirms that a heterogeneous source and drain embedded structure is a promising candidate for high-density and low-power DRAM technologies. [ABSTRACT FROM AUTHOR]

The basic operation of BJT-based floating-body 1T DRAM cells on SO! is analyzed with supportive numerical device simulation. Extreme sensitivity of the charging process (write "1") to the offset (ΔtWB) between the word-line and bit-line voltage pulses is revealed and explained. The necessity of a positive ΔtWB for successful write "1" is related to establishing a high gate capacitance, which is the predominant charge-storage element in the BJT-based cell. Such charging underlies why a fully depleted (FD) cell, e.g., a FinFET, can work for BJT-based DRAM, without an independent bias for accumulation charge that is necessary in conventional FD-MOSFET DRAM cells for charge storage and data sensing. Furthermore, a bulk-accumulation effect in the BJT-based DRAM cell is revealed and described. It undermines the BJT operation and leads to ineffective charging and significant loss of sense margin when the cell body thickness is scaled. [ABSTRACT FROM AUTHOR]

The basic concept of a simplified and easily manufacturable version of the two-transistor floating-body/gate DRAM cell (FBGC) is proposed and demonstrated via simulation and fabrication/experiment. Converting the charge-storage transistor (Ti) to a gated diode enables easy and direct connection of its body to the gate of the sensing transistor in conventional planar SOI CMOS and in FinFET technologies, and also reduces the cell size. Numerical simulations show that the new cell can yield a much better signal margin and dissipate much less power than the one-transistor floating-body DRAM cells currently being assessed. A FinFET-based prototype of the new cell provides experimental corroboration of these features. [ABSTRACT FROM AUTHOR]

Unified random access memory (URAM) is demon- strated for the first time. The novel partially depleted (PD) SONOS FInFET provides unified function of a high-speed capacitorless iT DRAM and a nonvolatile memory (NVM). The combination of an oxide/nitride/oxide (O/NIO) layer and a floating-body fa- cilitates URAM operation in PD SONOS FinFETs. An NVM function is achieved by FN tunneling into the OINIO stack and, a iT-DRAM function is achieved by excessive-hole accumulation in the PD body. The fabricated PD SONOS FinFET shows retention time exceeding 10 years for NVM operation and program/erase time below 6 ns for iT-DRAM in a single-cell transistor. These two memory functions are guaranteed without disturbance between them. [ABSTRACT FROM AUTHOR]

A bulk FinFET-based unified-RAM (URAM) cell technology is demonstrated for the fusion of a nonvolatile-memory (NVM) and capacitorless 1T-DRAM. An oxide/nitride/oxide layer and a floating-body are combined to perform a URAM operation in a single transistor. A buried n-well technology for NMOS allows hole accumulation for the 1T-DRAM operation in a p-type bulk substrate. The bulk FinFET URAM offers a cost-effective and fully compatible process with a conventional FinFET SONOS, and it also expedites heat dissipation. Highly reliable NVM and high-speed 1T-DRAM operation are confirmed, and it was also verified that there is no disturbance between the two memory functions. [ABSTRACT FROM AUTHOR]

Abstract: CMOS evolution at Moore’s law speed modulated by market demand is facing extrinsic and intrinsic limitations. Main extrinsic drawback is process variability affecting yield production. Solutions to address this point are focused on design and integration at dice level. Intrinsic limitations are usually summarized through the term Short Channel Effects, SCE. To overcome parasitic SCE, device engineers consider building aggressively shrink CMOS transistors on thin silicon film. These devices, allow a better electrostatic potential control. New memory cell architecture can be evaluated on thin film technologies following CMOS evolution. Recent literature reports many efforts to utilize floating body effect to enable volatile and non volatile memories. In this study we present how one transistor built on thin film can be considered for volatile and non volatile memory applications. Memory effects are electrically evaluated on thin Buried Oxide, BOx, Fully Depleted SOI, FDSOI, devices of sub 75nm gate length. [Copyright &y& Elsevier]