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A novel single-transistor configuration active pixel image sensor (APS) has been investigated in this paper. This device can realize the functions of the conventional 3T CMOS image sensor. In this paper, the basic performances including transient simulation, potential changes, and read endurance of the 1T image sensor will be discussed. Different from the conventional 3T CMOS image sensor, holes are used as signal charges in the proposed device. Comparison with the conventional 3T APS will be discussed as well.

An n-ZnO nanowires/p-Si heterojunction with amorphous ZnO seed layer prepared by atomic layer deposition is fabricated and its characteristics are investigated. After deposition of ZnO seed layer, the ZnO nanowire arrays are grown by the hydrothermal method. The influence of seed layer annealing on the nanowires is studied by X-ray diffraction spectrum results of the seed layer and corresponding nanowire arrays. Current-voltage measurements are taken at different temperatures to analyze the electrical characteristics of the heterojunction. The device shows high on/off current ratio, good reverse breakdown characteristic and high carrier injection efficiency.

A 1T silicon-based image sensor has been investigated in this paper. This device can fully accomplish the functions of the conventional 3T CMOS image sensor. In this paper, the basic performances including the dynamic range, read margin (signal-to-noise ratio) and information storage of the 1-T image sensor have been discussed. The applied voltages have been studied in detail, including the reset operation, read operation and exposure operation. The advantage of this device is the minimized cell size. The structure with a photo-diode integrated into the 1-T image sensor may give a higher density in the same chip area while the performance is not degraded. With more pixels in the same area, the fill factor will be raised to a large extent, and the resolution can be further improved.

A novel memory device with dual floating-gate is investigated in this paper. The fabrication process of this device is compatible with the standard logic CMOS process flow using single gate poly. It can store 2 bits in a single cell without increasing the cell size. This study provides the fabrication process flow of the dual floating-gate devices. The transfer characteristics, programming, reading, and erasing performances are investigated. The crosstalk between these two floating-gates is also studied. Simulation results show a prosperous prospect of this device. It is promising for high density embedded FLASH applications.