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Neuromorphic computing offers a promising solution to overcome the von Neumann bottleneck, where the separation between the memory and the processor poses increasing limitations of latency and power consumption. For this purpose, a device with analog switching for weight update is necessary to implement neuromorphic applications. In the diversity of emerging devices postulated as synaptic elements in neural networks, RRAM emerges as a standout candidate for its ability to tune its resistance. The learning accuracy of a neural network is directly related to the linearity and symmetry of the weight update behavior of the synaptic element. However, it is challenging to obtain such a linear and symmetrical behavior with RRAM devices. Thus, extensive research is currently devoted at different levels, from material to device engineering, to improve the linearity and symmetry of the conductance update of RRAM devices. In this work, the experimental results based on different programming pulse conditions of RRAM devices are presented, considering both voltage and current pulses. Their suitability for application as analog RRAM-based synaptic devices for neuromorphic computing is analyzed by computing an asymmetric nonlinearity factor., This work was supported in part by Spanish MCIN/AEI /10.13039/501100011033/FEDER, under Projects PID2022-141391OB-C22 and PID2022-139586NB-C42., Postprint (published version)

This work presents a RRAM-bias current starved ring oscillator (CSRO) as TRNG, where the cycle-to-cycle variability of a RRAM device is exploited as source of randomness. A simple voltage divider composed of this RRAM and a resistor is considered to bias the gate terminal of the extra transistor of every current starved (CS) inverter of the RO. In this way, the delay of the inverters is modified, deriving an unpredictable oscillation frequency every time the RRAM switches to the HRS. The oscillation frequency is finally leveraged to extract the sequence of random bits. The design is simple and add low area overhead. Experimental measurements are performed to analyze the cycle-to-cycle variability in the HRS. The very same measurements are subsequently used to validate the TRNG by means of electrical simulations. The obtained results passed all the NIST tests without the need for post-processing., This work was supported by the Spanish MCIN/AEI/10.13039/501100011033 under Project PID2019-103869RB-C33. The work of M. B. González was supported by the Ramón y Cajal under Grant RYC2020-030150-I., Peer Reviewed, Postprint (published version)

Neuromorphic computing offers a promising solution to overcome the von Neumann bottleneck, where the separation between the memory and the processor poses increasing limitations of latency and power consumption. For this purpose, a device with analog switching for weight update is necessary to implement neuromorphic applications. In the diversity of emerging devices postulated as synaptic elements in neural networks, RRAM emerges as a standout candidate for its ability to tune its resistance. The learning accuracy of a neural network is directly related to the linearity and symmetry of the weight update behavior of the synaptic element. However, it is challenging to obtain such a linear and symmetrical behavior with RRAM devices. Thus, extensive research is currently devoted at different levels, from material to device engineering, to improve the linearity and symmetry of the conductance update of RRAM devices. In this work, the experimental results based on different programming pulse conditions of RRAM devices are presented, considering both voltage and current pulses. Their suitability for application as analog RRAM-based synaptic devices for neuromorphic computing is analyzed by computing an asymmetric nonlinearity factor.

Hardware-based security primitives like True Random Number Generators (TRNG) have become a crucial part in protecting data over communication channels. With the growth of internet and cloud storage, TRNGs are required in numerous cryptographic operations. On the other hand, the inherently dense structure and low power characteristics of emerging nanoelectronic technologies such as resistive-switching memories (RRAM) make them suitable elements in designing hardware security modules integrated in CMOS ICs. In this paper, a memristor based TRNG is presented by leveraging the high stochasticity of RRAM resistance value in OFF (High Resistive) state. In the proposal, one or two devices can be used depending on whether the objective is focused on saving area or obtaining a higher random bit frequency generation. The generated bits, based on a combination of experimental measurements and SPICE simulations, passed all 15 National Institute of Standards and Technology (NIST) tests and achieved a throughput of tens of MHz., Postprint (published version)

A methodology to estimate the device temperature in resistive random access memories (RRAMs) is presented. Unipolar devices, which are known to be highly influenced by thermal effects in their resistive switching operation, are employed to develop the technique. A 3D RRAM simulator is used to fit experimental data and obtain the maximum and average temperatures of the conductive filaments (CFs) that are responsible for the switching behavior. It is found that the experimental CFs temperature corresponds to the maximum simulated temperatures obtained at the narrowest sections of the CFs. These temperature values can be used to improve compact models for circuit simulation purposes.

The application of constant electrical stress to a metal–insulator-semiconductor (MOS) or metal–insulator-metal (MIM) structure can generate multiple breakdown events in the dielectric film. Very often, these events are detected as small jumps in the current–time characteristic of the device under test and can be treated from the stochastic viewpoint as a counting process. In this letter, a wide variety of standard reliability growth models for this process are assessed in order to determine which option provides the best simulation results compatible with the experimental observations. For the generation of the breakdown event arrivals, two alternative stochastic methods for the power-law Poisson process are investigated: first, the inversion algorithm for the cumulative distribution function and second, an on-the-fly method based on the so-called rejection algorithm. Though both methods are equivalent, the first one is more appropriate for data analysis using spreadsheet calculations while the second one is highly suitable for circuit simulation environments like LTSpice. The connection of the selected nonhomogeneous Poisson process with the Weibull model for dielectric breakdown is also discussed.

This letter reports a compact SPICE model for the electron transport characteristics of Al2O3/HfO2-based nanolaminates for their use in multilevel one-time programmable (M-OTP) memories. The model comprises three simulation blocks corresponding to the electrical stimulus applied to the device, the equivalent circuit of the memory cell, and the events generator associated with the dielectric breakdown of the insulating layer. For a clear assessment of the quantum effects occurring in these structures, constant voltage stress was used as the primary electrical stimulus. The antifuse (AF) cell is represented by a combination of series and parallel resistances that account for the formation of filamentary conducting paths with quantum properties across the structure. The arrival of successive breakdown events is simulated using a power-law nonhomogeneous Poisson process. Our study indicates that a M-OTP memory device operating in the quantum regime not only is feasible but also that its stochastic features are addressable by circuit simulations.

In this work, the unipolar resistive switching behaviour of Ni/HfO2/Si(n+) devices is studied. The structures are characterized using both current and voltage sweeps, with the device resistance and its cycle-to-cycle variability being analysed in each case. Experimental measurements indicate a clear improvement on resistance states stability when using current sweeps to induce both set and reset processes. Moreover, it has been found that using current to induce these transitions is more efficient than using voltage sweeps, as seen when analysing the device power consumption. The same results are obtained for devices with a Ni top electrode and a bilayer or pentalayer of HfO2/Al2O3 as dielectric. Finally, kinetic Monte Carlo and compact modelling simulation studies are performed to shed light on the experimental results.

In this work, we investigate the effects related to the etching process of the W bottom electrode (BE) on the breakdown voltages and the resistive switching (RS) characteristics of TiN/Ti/HfO2/W memristors. Two different W-BE etching processes are compared: anisotropic dry etching and isotropic wet etching. In order to complete the analysis, scanning electron microscope inspections are used to investigate the profile of the patterned BE. Finally, the hysteretic current–voltage (I-V) characteristics are simulated using the Dynamic Memdiode Model (DMM).

Variability of the conduction characteristics of filamentary-type resistive switching devices or resistive RAMs (RRAMs) is a hot research topic both in academia and industry because it is currently considered one of the major showstoppers for the successful development and application of this technology. In this work, we thoroughly investigate the statistics of the cycle-to-cycle (C2C) variability observed in the experimental current–voltage (I-V) curves of HfO2-based memristive structures using the fitdistrplus package for the R language. This exploratory analysis allows us to identify which parametric probability distributions are the most suitable candidates for describing our data. This study involves graphical tools such as the density, skewness-kurtosis (S-K), and quantile–quantile (Q-Q) plots. The analysis is completed with the aid of goodness-of-fit statistics (Kolmogorov-Smirnov, Cramer-von Mises, Anderson-Darling) and criteria (Akaike's and Bayesian). The selected distributions are incorporated into the SPICE script of the quasi-static memdiode model for resistive switching devices and used for simulating uncorrelated C2C variability. Finally, a one-way sensitivity analysis is carried out in order to test the impact of the model parameters variation in the output characteristics of the device.

This work presents a resistive random access memory (RRAM)-bias current-starved ring oscillator (CSRO) as true random number generator (TRNG), where the cycle-to-cycle variability of an RRAM device is exploited as source of randomness. A simple voltage divider composed of this RRAM and a resistor is considered to bias the gate terminal of the extra transistor of every current starved (CS) inverter of the ring oscillator (RO). In this way, the delay of the inverters is modified, deriving an unpredictable oscillation frequency every time the RRAM switches to the high resistance state (HRS). The oscillation frequency is finally leveraged to extract the sequence of random bits. The design is simple and adds low area overhead. Experimental measurements are performed to analyze the cycle-to-cycle variability in the HRS. The very same measurements are subsequently used to validate the TRNG by means of electrical simulations. The obtained results passed all the National Institute of Standards and Technology randomness tests (NIST) tests without the need for postprocessing.

Hardware-based security primitives like True Random Number Generators (TRNG) have become a crucial part in protecting data over communication channels. With the growth of internet and cloud storage, TRNGs are required in numerous cryptographic operations. On the other hand, the inherently dense structure and low power characteristics of emerging nanoelectronic technologies such as resistive-switching memories (RRAM) make them suitable elements in designing hardware security modules integrated in CMOS ICs. In this paper, a memristor based TRNG is presented by leveraging the high stochasticity of RRAM resistance value in OFF (High Resistive) state. In the proposal, one or two devices can be used depending on whether the objective is focused on saving area or obtaining a higher random bit frequency generation. The generated bits, based on a combination of experimental measurements and SPICE simulations, passed all 15 National Institute of Standards and Technology (NIST) tests and achieved a throughput of tens of MHz.

Resistive memories are outstanding electron devices that have displayed a large potential in a plethora of applications such as nonvolatile data storage, neuromorphic computing, hardware cryptography, etc. Their fabrication control and performance have been notably improved in the last few years to cope with the requirements of massive industrial production. However, the most important hurdle to progress in their development is the so-called cycle-to-cycle variability, which is inherently rooted in the resistive switching mechanism behind the operational principle of these devices. In order to achieve the whole picture, variability must be assessed from different viewpoints going from the experimental characterization to the adequation of modeling and simulation techniques. Herein, special emphasis is put on the modeling part because the accurate representation of the phenomenon is critical for circuit designers. In this respect, a number of approaches are used to the date: stochastic, behavioral, mesoscopic.., each of them covering particular aspects of the electron and ion transport mechanisms occurring within the switching material. These subjects are dealt with in this review, with the aim of presenting the most recent advancements in the treatment of variability in resistive memories.

In this work, an experimental analysis of the resistive switching behavior of TiN/Ti/Al2O3/W memristors is presented. The main focus is on the analysis of the variability of the key parameters during long series of cycles, using both sweep and pulsed voltage measurement sequences. In addition, the correlation of the resistive switching parameters between subsequent cycles has been investigated. The results demonstrate that memristors based on Ti/Al2O3 exhibit a low cycle-to-cycle variability between consecutive cycles, indicating their potential use for emerging applications.

The ballistic conduction through narrow constrictions connecting charge reservoirs exhibits conductance quantization effects. Since the quantum of conductance (Formula presented.) is only related to fundamental constants of nature, these effects might allow the implementation of a standard of resistance, fulfilling the requirements of the 2019 revised International System of Units. Moreover, this standard would be able to work at room temperature and without a magnetic field, thus allowing its on-chip implementation. In this work, the authors propose that breakdown filaments in thin oxide layers might be useful to this purpose. In particular, conductance quantization effects in nanolaminate Al2O3/HfO2 dielectrics are reported and the role of intrinsic values of conductance and extrinsic parasitic elements are analyzed. The fact that breakdown filaments are irreversible is an advantage due to their expected stability and to the lack of cycle-to-cycle variations (as compared to resistive switching devices). Although the reported sample-to-sample variations are still too large for a real application, there is room for improving the controlover breakdown filaments through material design and electroforming conditions. Provided that this control is achieved, an on-chip implementation of a resistance standard for the realization of self-calibrating electrical systems and equipment with zero-chain traceability would be possible.

Memristive devices have shown a great potential for non-volatile memory circuits and neuromorphic computing. For both applications it is essential to know the physical mechanisms behind resistive switching; in particular, the time response to external voltage signals. To shed light in these issues we have studied the role played by the applied voltage ramp rate in the electrical properties of TiN/Ti/HfO2/W metal-insulator-metal resistive switching devices. Using an ad hoc experimental set-up, the current-voltage characteristics were measured for ramp rates ranging from 100 mV s−1-1 MV s−1. These measurements were used to investigate in detail the set and reset transitions. It is shown that the highest ramp rates allow controlling the resistance values corresponding to the intermediate states at the very beginning of the reset process, which is not possible by means of standard quasistatic techniques. Both the set and reset voltages increase with the ramp rate because the oxygen vacancies movement is frequency dependent so that, when the ramp rate is high enough, the conductive filaments neither fully form nor dissolve. In agreement with Chua’s theory of memristive devices, this effect causes the device resistance window to decrease as the ramp rate increases, and even to vanish for very high ramp rates. Remarkably, we demonstrate that the voltage ramp rate can be straightforwardly used to control the conductance change of the switching devices, which opens up a new way to program the synaptic weights when using these devices to mimic synapses for neuromorphic engineering applications. Moreover, the data obtained have been compared with the predictions of the dynamic memdiode model.

A revision of the different numerical techniques employed to extract resistive switching (RS) and modeling parameters is presented. The set and reset voltages, commonly used for variability estimation, are calculated for different resistive memory technologies. The methodologies to extract the series resistance and the parameters linked to the charge-flux memristive modeling approach are also described. It is found that the obtained cycle-to-cycle (C2C) variability depends on the numerical technique used. This result is important, and it implies that when analyzing C2C variability, the extraction technique should be described to perform fair comparisons between different resistive memory technologies. In addition to the use of extensive experimental data for different types of resistive memories, we have also included kinetic Monte Carlo (kMC) simulations to study the formation and rupture events of the percolation paths that constitute the conductive filaments (CF) that allow resistive switching operation in filamentary unipolar and bipolar devices.

In recent years, several materials and metal-insulator-metal devices are being intensively studied as prospective non-volatile memories due to their resistive switching effect. In this work, thickness-dependent resistive switching polarity was observed in TiN/Ti/HfO2/Pt structures as the sign of the voltages at which SET and RESET occur depended on the film thickness. A thorough revision of the previous literature on bipolar resistive switching polarity changes is made in order to condense previous knowledge of the subject in a brief and comprehensible way and explain the experimental measurements. The different resistive switching polarities occur in a similar voltage range, which is a new finding when compared to precedent research on the subject. A hypothesis is proposed to explain the change in resistive switching polarity, based on the assumption that polarity change is due to filament disruption occurring at different interfaces.

TiN/Ti/HfO2/Pt resistive switching devices have been fabricated, measured, and modeled. After programming the devices in the low resistance state, the current-voltage characteristic below the reset switching voltage was measured at different temperatures (from 90 to 350 K). A weak but complex temperature dependence was obtained for several voltage regimes. These memristors belong to a wider set known as valence change memories, whose conductance is determined by the formation of conductive filaments (CFs) linked to a high density of oxygen vacancies in a dielectric sandwiched between two metal electrodes. This usually leads to ohmic conduction in the low resistance state. However, a non-linear current dependence has been also observed in the measured devices, in addition to symmetric current-voltage curves for positive and negative biases in the 0-0.6 V voltage range. Three different thermal dependences have been considered for explaining the whole set of experimental data. Two of them are linked to ohmic filamentary conduction; the CF shows a conductivity enhancement due to thermally activated mechanisms at low temperatures; on the contrary, a CF conductivity degradation is observed at the higher temperatures. Finally, an additional slightly higher value for the non-linear current component as the temperature rises has also been taken into account. A semiempirical compact model has been implemented including these conduction mechanisms and their corresponding temperature dependences, the device has been simulated in LT-Spice and the experimental currents have been correctly reproduced.

© 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works., Model-based simulation is one of the effective methods of scientific research. The inherent variability of resistive switching mechanisms has been an obstacle for the massive commercial implementation of the resistive random access memory (RRAM) devices. In this work, we simulated the resistive switching behavior based on an existing RRAM Verilog-A model, in which the simulated switching parameters demonstrated a satisfactory fit with the experimental data by introducing variability into the model. Moreover, a potential application of the troublesome variability was explored in the serial configuration of two RRAM devices, a cell which had been demonstrated to generate unpredictable bits with potential applications in hardware security. Realistic simulation of RRAM based circuits is key for the future development of RRAM based applications., Peer Reviewed, Postprint (published version)

In this letter, the serial configuration of two RRAMs is used as a basic cell to generate an unpredictable bit. The basis of the operation considers starting from the Low Resistive State (LRS) in both devices (initialization step), then, one of them is switched to the High Resistive State (HRS) (bit generation step) without knowing, in advance, which one is the switching device (unmasking step). In this proposal, the larger resistance variability of HRS compared to LRS is considered to improve the masking performance of the cell (masking step). The presented experimental results are a proof-of-concept of the applicability of the proposal., Peer Reviewed, Postprint (published version)