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Dynamic Binary Modification (DBM) is a technique that allows an application to be modified at runtime transparently, as it executes at the machine instruction level. DBM is used in many areas such as virtualisation, instrumentation, program analysis and translation. Dynamic Binary Modification, however, has an associated performance penalty. A DBM system has many of its internal components which are architecture-specific. The release of a new version of the Arm architecture (Armv8) opened the door to research on optimisations for this specific architecture. Moreover, Arm systems are available in a range of microarchitectures; from low-power in-order processors, to more aggressive out-of-order processors. Research indicates that the microarchitecture of a system has an impact on the performance of DBM systems. The thesis aims to investigate performance optimisations for the 64-bit Arm architecture across a range of microarchitectures. The MAMBO DBM system was ported to 64-bit Arm and optimisations from the literature were implemented in it. The evaluation of this implementation shows the execution time geometric mean overheads on SPEC CPU2006 of 12.1% to 20.4% on the 5 different microarchitectures evaluated. Furthermore, an optimised code layout for traces and a new runtime algorithm to generate it are proposed. These optimisations reduce the overhead on all the Arm systems evaluated to 9.3% to 12.1%. The major source of overhead for DBMs comes from handling indirect branches. Indirect Branch Inlining (IBI) is a mechanism that attempts to minimise this overhead by using predictions for the target of an indirect branch. A new predictor is proposed (Trace Restricted IBI (TRIBI)) and evaluated, which manages to reduce the overhead in all microarchitectures evaluated to 7.2% to 10.7%.