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Negative differential resistance (NDR) behavior observed in several transition metal oxides is crucial for developing next-generation memory devices and neuromorphic computing systems. NbO2-based memristors exhibit two regions of NDR at room temperature, making them promising candidates for such applications. Despite this potential, the physical mechanisms behind the onset and the ability to engineer these NDR regions remain unclear, hindering further development of these devices for applications. This study employed electrical transport and ultra-low frequency noise spectroscopy measurements to investigate two distinct NDR phenomena in nanoscale thin films of NbO2. By analyzing the residual current fluctuations as a function of time, we find spatially inhomogeneous and non-linear conduction near NDR-1 and a two-state switching near NDR-2, leading to an insulator-to-metal (IMT) transition. The power spectral density of the residual fluctuations exhibits significantly elevated noise magnitudes around both NDR regions, providing insights into physical mechanisms and device size scaling for electronic applications. A simple theoretical model, based on the dimerization of correlated insulators, offers a comprehensive explanation of observed transport and noise behaviors near NDRs, affirming the presence of non-linear conduction followed by an IMT connecting macroscopic device response to transport signatures at atomic level.

The electrical properties and performance characteristics of niobium dioxide (NbO$_\mathrm{2}$)-based memristive devices are examined at cryogenic temperatures. Sub-stoichiometric Nb$_\mathrm{2}$O$_\mathrm{5}$ was deposited via magnetron sputtering and patterned in microscale (2$\times$2 - 15$\times$15 $\mu$m$^2$) cross-bar Au/Ru/NbO$_\mathrm{x}$/Pt devices and electroformed at 3-5 V to make NbO$_\mathrm{2}$ filaments. At cryogenic temperatures, the threshold voltage ($V_\mathrm{th}$) increased by more than a factor of 3. The hold voltage ($V_\mathrm{h}$) was significantly lower than the threshold voltage for fast voltage sweeps (200 ms per measurement). If the sample is allowed to cool between voltage measurements, the hold voltage increases, but never reaches the threshold voltage, indicating the presence of non-volatile Nb$_\mathrm{2}$O$_\mathrm{5}$ in the filament. The devices have an activation energy of $E_a \approx 1.4$ eV, lower than other NbO$_\mathrm{2}$ devices reported. Our works shows that even nominally ``bad" memristive devices can be improved by reducing the leakage current and increases the sample resistance at cryogenic temperatures., Comment: 16 pages, 5 figures

Significant research has focused on low-power stochastic devices built from memristive materials. These devices foster neuromorphic approaches to computational efficiency enhancement in merged biomimetic and CMOS architectures due to their ability to phase transition from a dielectric to a metal at an increased temperature. Niobium dioxide has a volatile memristive phase change that occurs $\sim$800$^\circ$C~that makes it an ideal candidate for future neuromorphic electronics. A straightforward optical system has been developed on a horizontal tube furnace for \emph{in situ} spectral measurements as an as-grown \NbtOf\ film is annealed and ultimately crystallizes as \NbOt. The system measures the changing spectral transmissivity of \NbtOf\ as it undergoes both reduction and crystallization processes. We were also able to measure the transition from metallic-to-non-metallic \NbOt\ during the cooldown phase, which is shown to occur about 100$^\circ$C~ lower on a sapphire substrate than fused silica. After annealing, the material properties of the \NbtOf\ and \NbOt\ were assessed via X-ray photoelectron spectroscopy, X-ray diffraction, and 4-point resistivity, confirming that we have made crystalline \NbOt.

Memristors provide a tempting solution for weighted synapse connections in neuromorphic computing due to their size and non-volatile nature. However, memristors are unreliable in the commonly used voltage-pulse-based programming approaches and require precisely shaped pulses to avoid programming failure. In this paper, we demonstrate a current-limiting-based solution that provides a more predictable analog memory behavior when reading and writing memristive synapses. With our proposed design READ current can be optimized by about 19x compared to the 1T1R design. Moreover, our proposed design saves about 9x energy compared to the 1T1R design. Our 3T1R design also shows promising write operation which is less affected by the process variation in MOSFETs and the inherent stochastic behavior of memristors. Memristors used for testing are hafnium oxide based and were fabricated in a 65nm hybrid CMOS-memristor process. The proposed design also shows linear characteristics between the voltage applied and the resulting resistance for the writing operation. The simulation and measured data show similar patterns with respect to voltage pulse-based programming and current compliance-based programming. We further observed the impact of this behavior on neuromorphic-specific applications such as a spiking neural network

Reservoir computing is a subfield of machine learning in which a complex system, or 'reservoir,' uses complex internal dynamics to non-linearly project an input into a higher-dimensional space. A single trainable output layer then inspects this high-dimensional space for features relevant to perform the given task, such as a classification. Initially, reservoirs were often constructed from recurrent neural networks, but reservoirs constructed from many different elements have been demonstrated. Elementary cellular automata (CA) are one such system which have recently been demonstrated as a powerful and efficient basis which can be used to construct a reservoir. To investigate the feasibility and performance of a monolithic reservoir computing circuit with a fully integrated, programmable read-out layer, we designed, fabricated, and tested a full-custom reservoir computing circuit. This design, the cellular memristive-output reservoir (CMOR), is implemented in 65-nm CMOS technology with integrated front-end-of-the-line (FEOL) resistive random-access memory (ReRAM) used to construct a trainable output layer. We detail the design of this system and present electrical test results verifying its operation and capability to carry out non-linear classifications.

Artificial neural networks normally require precise weights to operate, despite their origins in biological systems, which can be highly variable and noisy. When implementing artificial networks which utilize analog 'synaptic' devices to encode weights, however, inherent limits are placed on the accuracy and precision with which these values can be encoded. In this work, we investigate the effects that inaccurate synapses have on spiking neurons and spiking neural networks. Starting with a mathematical analysis of integrate-and-fire (IF) neurons, including different non-idealities (such as leakage and channel noise), we demonstrate that noise can be used to make the behavior of IF neurons more robust to synaptic inaccuracy. We then train spiking networks which utilize IF neurons with and without noise and leakage, and experimentally confirm that the noisy networks are more robust. Lastly, we show that a noisy network can tolerate the inaccuracy expected when hafnium-oxide based resistive random-access memory is used to encode synaptic weights.