24 results on '"Cabo, Guillem"'
Search Results
2. SafeSoftDR: A Library to Enable Software-based Diverse Redundancy for Safety-Critical Tasks
- Author
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Mazzocchetti, Fabio, Alcaide, Sergi, Bas, Francisco, Benedicte, Pedro, Cabo, Guillem, Chang, Feng, Fuentes, Francisco, and Abella, Jaume
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Computer Science - Hardware Architecture - Abstract
Applications with safety requirements have become ubiquitous nowadays and can be found in edge devices of all kinds. However, microcontrollers in those devices, despite offering moderate performance by implementing multicores and cache hierarchies, may fail to offer adequate support to implement some safety measures needed for the highest integrity levels, such as lockstepped execution to avoid so-called common cause failures (i.e., a fault affecting redundant components causing the same error in all of them). To respond to this limitation, an approach based on a software monitor enforcing some sort of software-based lockstepped execution across cores has been proposed recently, providing a proof of concept. This paper presents SafeSoftDR, a library providing a standard interface to deploy software-based lockstepped execution across non-natively lockstepped cores relieving end-users from having to manage the burden to create redundant processes, copying input/output data, and performing result comparison. Our library has been tested on x86-based Linux and is currently being integrated on top of an open-source RISC-V platform targeting safety-related applications, hence offering a convenient environment for safety-critical applications., Comment: FORECAST 2022 Functional Properties and Dependability in Cyber-Physical Systems Workshop (held jointly with HiPEAC Conference)
- Published
- 2022
3. SafeDX: Standalone Modules Providing Diverse Redundancy for Safety-Critical Applications
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Canal, Ramon, Bas, Francisco, Alcaide, Sergi, Cabo, Guillem, Benedicte, Pedro, Fuentes, Francisco, Chang, Feng, Lasfar, Ilham, Abella, Jaume, Goos, Gerhard, Founding Editor, Hartmanis, Juris, Founding Editor, Bertino, Elisa, Editorial Board Member, Gao, Wen, Editorial Board Member, Steffen, Bernhard, Editorial Board Member, Yung, Moti, Editorial Board Member, Orailoglu, Alex, editor, Reichenbach, Marc, editor, and Jung, Matthias, editor
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- 2022
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4. DVINO: A RISC-V Vector Processor Implemented in 65nm Technology
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Cabo, Guillem, primary, Candon, Gerard, additional, Carril, Xavier, additional, Doblas, Max, additional, Dominguez, Marc, additional, Gonzalez, Alberto, additional, Hernandez, Cesar, additional, Jimenez, Victor, additional, Kostalampros, Vatistas, additional, Langarita, Ruben, additional, Leyva, Neiel, additional, Lopez-Paradis, Guillem, additional, Mendoza, Jonnatan, additional, Minervini, Francesco, additional, Pavon, Julian, additional, Ramirez, Cristobal, additional, Rodas, Narcis, additional, Reggiani, Enrico, additional, Rodriguez, Mario, additional, Rojas, Carlos, additional, Ruiz, Abraham, additional, Soria, Victor, additional, Suanes, Alejandro, additional, Vargas, Ivan, additional, Figueras, Roger, additional, Fontova, Pau, additional, Marimon, Joan, additional, Montabes, Victor, additional, Cristal, Adrian, additional, Hernandez, Carles, additional, Martinez, Ricardo, additional, Moreto, Miquel, additional, Moll, Francesc, additional, Palomar, Oscar, additional, Ramirez, Marco A., additional, Rubio, Antonio, additional, Sacristan, Jordi, additional, Serra-Graells, Francesc, additional, Sonmez, Nehir, additional, Teres, Lluis, additional, Unsal, Osman, additional, Valero, Mateo, additional, and Villa, Luis, additional
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- 2022
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5. SafeX: Open Source Hardware and Software Components for Safety-Critical Systems
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Alcaide, Sergi, primary, Cabo, Guillem, additional, Bas, Francisco, additional, Benedicte, Pedro, additional, Fuentes, Francisco, additional, Chang, Feng, additional, Lasfar, Ilham, additional, Canal, Ramon, additional, and Abella, Jaume, additional
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- 2022
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6. SafeDE: A Low-Cost Hardware Solution to Enforce Diverse Redundancy in Multicores
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Bas, Francisco, primary, Alcaide, Sergi, additional, Cabo, Guillem, additional, Benedicte, Pedro, additional, and Abella, Jaume, additional
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- 2022
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7. De-RISC: A Complete RISC-V Based Space-Grade Platform
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Wessman, Nils-Johan, primary, Malatesta, Fabio, additional, Ribes, Stefano, additional, Andersson, Jan, additional, Garcia-Vilanova, Antonio, additional, Masmano, Miguel, additional, Nicolau, Vicente, additional, Gomez, Paco, additional, Rhun, Jimmy Le, additional, Alcaide, Sergi, additional, Cabo, Guillem, additional, Bas, Francisco, additional, Benedicte, Pedro, additional, Mazzocchetti, Fabio, additional, and Abella, Jaume, additional
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- 2022
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8. SafeDM: a Hardware Diversity Monitor for Redundant Execution on Non-Lockstepped Cores
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Bas, Francisco, primary, Benedicte, Pedro, additional, Alcaide, Sergi, additional, Cabo, Guillem, additional, Mazzocchetti, Fabio, additional, and Abella, Jaume, additional
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- 2022
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9. SafeSU-2: a Safe Statistics Unit for Space MPSoCs
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Cabo, Guillem, primary, Alcaide, Sergi, additional, Hernandez, Carles, additional, Benedicte, Pedro, additional, Bas, Francisco, additional, Mazzocchetti, Fabio, additional, and Abella, Jaume, additional
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- 2022
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10. De-RISC: Dependable Real-time RISC-V Infrastructure for Safety-critical Space and Avionics Computer Systems
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G��mez-Molinero, Francisco, Masmano, Miguel, Nicolau, Vicente, Wessman, Nils-Johan, Andersson, Jan, Le Rhun, Jimmy, Cabo, Guillem, Benedicte, Pedro, Alcaide, Sergi, and Abella, Jaume
- Subjects
NOEL-V ,XtratuM hypervisor ,RISC-V ,aerospace - Abstract
The world market for aviation and space computing systems faces a significant shift caused by the loss of momentum of the traditionally used PowerPC and SPARC instruction set architectures in the commercial domain. This means that the space industry is not able to leverage training, software tools, etc. from the commercial domain and this fuels a need to shift to architectures present in larger commercial markets. The De-RISC project brings together leading European entities within the areas of fault-tolerant microprocessors, hypervisors, embedded safety-critical software and mixed-criticality systems in an effort to commercialize a complete technology stack consisting of an FPGA space grade development board, system-on-chip design and software stack. The goal is to create a platform for the aerospace industries implementing the open RISC-V microprocessor instruction set architecture together with specific features to address the needs of the target industries and to adopt modern commercial technology to allow leveraging technology development from other domains., {"references":["RISC-V Foundation. https://riscv.org/, accessed in May 2021.","Cobham Gaisler. \"NOEL-V Processor\", https://www.gaisler.com/noel-v, accessed in May 2021.","fentISS. \"XtratuM\", https://fentiss.com/products/hypervisor/, accessed in May 2021.","\"De-RISC: Dependable Real-time Infrastructure for Safety-critical Computer\", http://www.derisc- project.eu/, accessed in May 2021.","Paco Gómez Molinero, Javier Coronel Parada, Miguel Masmano Tello, \"XtratuM: A space qualified Hypervisor for LEON-based Computers\", GR740 User Day at ESTEC, 28th November 2019.","Cobham Gaisler. \"GR740 Quad-Core LEON4 SPARC V8 Processor\", https://www.gaisler.com/gr740, accessed in May 2021.","fentISS, \"LithOS\", https://fentiss.com/products/lithos/, accessed in May 2021.","Enrico Mezzetti, Leonidas Kosmidis, Jaume Abella, Francisco J. Cazorla, \"High-Integrity Performance Monitoring Units in Automotive Chips for Reliable Timing V&V\", in IEEE Micro, vol. 38, no. 1, pp. 56- 65, January/February 2018.","Javier Jalle, Mikel Fernandez, Jaume Abella, Jan Andersson, Matthieu Patte, Luca Fossati, Marco Zulianello, Francisco J. Cazorla, \"Contention-aware performance monitoring counter support for real-time MPSoCs\", 2016 11th IEEE Symposium on Industrial Embedded Systems (SIES), Krakow, 2016, pp. 1-10.","L. Pomante, D. Andreetti, F. Federici, V. Muttillo, D. Pascucci, \"Analysis and design of a Command & Data Handling platform based on the LEON4 multicore processor and PikeOS hypervisor\", DAta Systems In Aerospace – DASIA 2017.","Julien Galizzi, Jean-Jacques Metge, Paul Arberet, Eric Morand, Fabien Vigeant, et al.. \"LVCUGEN (TSP-based solution) and first porting feedback\", Embedded Real Time Software and Systems (ERTS2012), Feb 2012, Toulouse, France."]}
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- 2021
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11. GPU4S (GPUs for Space): Are we there yet?
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Kosmidis, Leonidas, Rodriguez-Ferrandez, Iván, Jover-Alvarez, Alvaro, Cabo, Guillem, Alcaide, Sergi, Lachaize, Jérôme, Notebaert, Olivier, Certain, Antoine, and Steenari, David
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obdp2021 ,obdp ,on-board processing - Abstract
In this contribution, we provide an overview of the results and lessons learnt from the on-going ESA-funded GPU4s project (GPU for Space) performed by the BSC as a prime and ADS as subcontractor. Embedded GPUs can provide significant computational power at a low-power for large amounts of data, allowing the use of software for on-board processing. They allow more flexibility, easier reconfiguration compared to FPGAs and can support several different processing tasks through reuse of compute resources. Moreover, they can leverage an abundance of specialised developers, familiar with widely-used programming models, resulting in an overall lower cost. The purpose of this exploratory project is to address the increased needs for on-board processing performance of future missions, exploring the possibility of using embedded GPUs in space and studying the initial steps required for their adoption. In particular, our goal is the evaluation of GPU IP for possible future space processors as well as the evaluation of COTS GPUs. We performed a survey of existing and future algorithms used in space across all divisions of ADS, to identify which domains expect higher needs for performance and whether their algorithms have good characteristics for GPU parallelisation. We concluded that most space algorithms are a good fit for the GPU programming model, something we confirmed also experimentally later. In another survey, we studied the available hardware solutions and their software ecosystem. We focused on embedded GPU IPs from European providers, to identify the most appropriate one for a radiation-hardened implementation in an ASIC or FPGA in the long term. Additionally, we covered the most important embedded COTS GPU solutions, to identify the most appropriate one for lower cost, short-term adoption. We also expanded our survey to open source IP and GPU-like solutions. From this extensive coverage we selected to benchmark a set of embedded GPUs. For this, we have defined GPU4S Bench [1], an open source embedded GPU benchmarking suite, consisting of algorithmic building blocks from multiple space domains, identified in our space survey. GPU4S Bench provides also the basis and optimised implementations of these algorithms for GPUs and Multi-core CPUs used in ESA’s OBPMark, an open source benchmarking suite for general on-board processing devices. In addition to these benchmarks, we ported complex space applications, such as the Euclid NIR, the image processing and CCSDS compression benchmarks from OBPMark, demonstrating that GPUs can benefit significantly existing and mainly future space processing, in terms of performance and power consumption, including efficiency. In our contribution we will present a summary of the obtained results. Finally, we identified issues such as radiation effect mitigation, thermal management and procurement of GPU devices, which need to be addressed for the adoption of GPUs in space, we proposed potential solutions and defined a roadmap. Overall, our conclusion is that embedded GPUs have a high potential for providing the performance needs of future missions, and can significantly reduce the cost, while offering new capabilities. [1] GPU4S Bench: Design and Implementation of an Open GPU Benchmarking Suite for Space On-board Processing: https://www.ac.upc.edu/app/research-reports/public/html/research_center_index-CAP-2019,en.html
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- 2021
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12. De-RISC: the First RISC-V Space-Grade Platform for Safety-Critical Systems
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Wessman, Nils-Johan, primary, Malatesta, Fabio, additional, Andersson, Jan, additional, Gomez, Paco, additional, Masmano, Miguel, additional, Nicolau, Vicente, additional, Rhun, Jimmy Le, additional, Cabo, Guillem, additional, Bas, Francisco, additional, Lorenzo, Ruben, additional, Sala, Oriol, additional, Trilla, David, additional, and Abella, Jaume, additional
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- 2021
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13. SafeTI: a Hardware Traffic Injector for MPSoC Functional and Timing Validation
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Sala, Oriol, primary, Alcaide, Sergi, additional, Cabo, Guillem, additional, Bas, Francisco, additional, Lorenzo, Ruben, additional, Benedicte, Pedro, additional, Trilla, David, additional, Gil, Guillermo, additional, Mazzocchetti, Fabio, additional, and Abella, Jaume, additional
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- 2021
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14. SafeDE: a flexible Diversity Enforcement hardware module for light-lockstepping
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Bas, Francisco, primary, Alcaide, Sergi, additional, Lorenzo, Ruben, additional, Cabo, Guillem, additional, Gil, Guillermo, additional, Sala, Oriol, additional, Mazzocchetti, Fabio, additional, Trilla, David, additional, and Abella, Jaume, additional
- Published
- 2021
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15. SafeSU: an Extended Statistics Unit for Multicore Timing Interference
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Cabo, Guillem, primary, Bas, Francisco, additional, Lorenzo, Ruben, additional, Trilla, David, additional, Alcaide, Sergi, additional, Moreto, Miquel, additional, Hernandez, Carles, additional, and Abella, Jaume, additional
- Published
- 2021
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16. An Academic RISC-V Silicon Implementation Based on Open-Source Components
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Abella, Jaume, primary, Bulla, Calvin, additional, Cabo, Guillem, additional, Cazorla, Francisco J., additional, Cristal, Adrian, additional, Doblas, Max, additional, Figueras, Roger, additional, Gonzalez, Alberto, additional, Hernandez, Carles, additional, Hernandez, Cesar, additional, Jimenez, Victor, additional, Kosmidis, Leonidas, additional, Kostalabros, Vatistas, additional, Langarita, Ruben, additional, Leyva, Neiel, additional, Lopez-Paradis, Guillem, additional, Marimon, Joan, additional, Martinez, Ricardo, additional, Mendoza, Jonnatan, additional, Moll, Francesc, additional, Moreto, Miquel, additional, Pavon, Julian, additional, Ramirez, Cristobal, additional, Ramirez, Marco A., additional, Rojas, Carlos, additional, Rubio, Antonio, additional, Ruiz, Abraham, additional, Sonmez, Nehir, additional, Soria, Victor, additional, Teres, Lluis, additional, Unsal, Osman, additional, Valero, Mateo, additional, Vargas, Ivan, additional, and Villa, Luis, additional
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- 2020
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17. De-RISC – Dependable Real-Time Infrastructure for Safety-Critical Computer Systems
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Barcelona Supercomputing Center, Gómez, Francisco, Masmano, Miguel, Nicolau, Vicente, Andersson, Jan, Le Rhun, Jimmy, Trilla, David, Gallego, Felipe, Cabo, Guillem, Abella Ferrer, Jaume, Barcelona Supercomputing Center, Gómez, Francisco, Masmano, Miguel, Nicolau, Vicente, Andersson, Jan, Le Rhun, Jimmy, Trilla, David, Gallego, Felipe, Cabo, Guillem, and Abella Ferrer, Jaume
- Abstract
Publicat en accés amb el permís de l'editor / Published in open access with the permission of the publisher., The space domain demands increased performance, reliable and easy to verify and validate platforms tomatch the requirements of highly autonomous missions and systems that need to undergo qualification and certification against safety guidelines, and be commercialized worldwide minimizing export restrictions. Unfortunately, commercial platforms either fail to match domainspecific requirements for space (e.g. safety requirements), are limited by US export regulations, or simply fail both sets of requirements. This paper introduces De-RISC, a novel HW/SW platform meeting space requirements for safety- and mission-critical applications by construction, with explicit support to ease performance validation and diagnosis, and based on the RISC-V instruction set architecture. The De-RISC platform, which builds upon fentISS’ XtratuM hypervisor and a Cobham Gaisler (CG) NOEL-V based MPSoC, will reach commercial maturity in 2022, and will be assessed against a space use case., This project has received funding from the European Union’s Horizon 2020 Research and Innovation programme under Grant Agreement EIC-FTI 869945., Peer Reviewed, Postprint (published version)
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- 2020
18. RTL design and implementation of a framebuffer for a RISC-V processor
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Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya. Departament de Ciències de la Computació, Barcelona Supercomputing Center, Moretó Planas, Miquel, Cabo, Guillem, Rodas Quiroga, Narcís, Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya. Departament de Ciències de la Computació, Barcelona Supercomputing Center, Moretó Planas, Miquel, Cabo, Guillem, and Rodas Quiroga, Narcís
- Abstract
El conjunt d'instruccions o ISA (de l'anglès instruction set architecture) RISC-V i la fundació que el recolza segueixen creixent ràpidament com una alternativa open-source per als dissenys hardware. Tot i que el software open-source ja representa una part important de totes les solucions software, el hardware open-source encara està començant a expandir-se. Abans d'això, el mercat estava format íntegrament per ISAs propietàries (la gran majoria provinents dels EUA) que el controlaven. Aquest Treball de Final de Grau mostra el disseny, implementació i el testing d'un framebuffer VGA pel processador RISC-V que s'està desenvolupant en el projecte DRAC del Barcelona Supercomputing Centre. En aquest document s'expliquen els diversos passos seguits i el raonament darrera les decisions preses., The RISC-V instruction set architecture (ISA) and the foundation that supports it continue to grow rapidly as an open-source alternative for hardware designs. Despite open-source software already being established as an important part of all the software solutions, open-source hardware has only recently begun to expand. Before that, the market was entirely made of proprietary ISAs (mostly from the US) that controlled it. This Final Degree Thesis shows the design, implementation and testing of a VGA (Video Graphics Array) framebuffer for the RISC-V processor being developed in the DRAC project by the Barcelona Supercomputing Centre. This document explains the various steps taken along the way and the reasoning behind the decisions that were taken.
- Published
- 2020
19. De-RISC - Dependable Real-Time Infrastructure for Safety-Critical Computer Systems.
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Gómez, Francisco, Masmano, Miguel, Nicolau, Vicente, Andersson, Jan, Le Rhun, Jimmy, Trilla, David, Gallego, Felipe, Cabo, Guillem, and Abella, Jaume
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COMPUTER systems ,EXPORT controls - Abstract
The space domain demands increased performance, reliable and easy to verify and validate platforms to match the requirements of highly autonomous missions and systems that need to undergo qualification and certification against safety guidelines, and be commercialized worldwide minimizing export restrictions. Unfortunately, commercial platforms either fail to match domainspecific requirements for space (e.g. safety requirements), are limited by US export regulations, or simply fail both sets of requirements. This paper introduces De-RISC, a novel HW/SW platform meeting space requirements for safety- and mission-critical applications by construction, with explicit support to ease performance validation and diagnosis, and based on the RISC-V instruction set architecture. The De-RISC platform, which builds upon fentISS' XtratuM hypervisor and a Cobham Gaisler (CG) NOEL-V based MPSoC, will reach commercial maturity in 2022, and will be assessed against a space use case. [ABSTRACT FROM AUTHOR]
- Published
- 2020
20. Explaining archaeological research with videogames:The case of Evolving Planet
- Author
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Rubio-Campillo, Xavier, Caro Saiz, Jorge, H. Pongiluppi, Guillem, Laborda Cabo, Guillem, Ramos Garcia, David, Mol, Angus, riese-Vandemeulebroucke, Csilla, Boom, Krijn, and Politopoulos, Aris
- Abstract
Archaeology has experienced a large number of innovations during recent decades. Geographical Information Systems, archeometry, or laser scanning are only some of the methodological advances of the discipline. However, the public image on how archaeology works is roughly the same than it was several years ago. Specifically, it is dominated by the sense of wonder generated by the discovery of ancient civilizations and objects typically portrayed in fiction works.Can we exploit this fascination for discovery while explaining what archaeology is really about? This approach would need to stablish links between scientific thinking and the type of puzzle-solving mystery typically portrayed in books and movies. We argue here that videogames are one of the best available tools to integrate these two concepts. On the one hand, their high level of interaction led by trial-and-error mechanisms makes them suitable to learn how science works. On the other hand, videogames are powerful narrative devices so they can be used to tell a story to the player.This work describes how these ideas were used to create Evolving Planet. This videogame was designed as the dissemination initiative of the research project SimulPast. The player takes the role of a future scientist studying the extinction of a sentient species in a distant planet. The use of science-fiction allowed us to portray topics such as evolution, technology and cooperation while solving the mystery on the disappearance of an entire civilization. At the same time the game mechanics are remarkably similar to the methods used in the project, and particularly to computer simulation. We explore here a diversity of challenges and decisions faced by the development team in the effort to explain our research methods while retaining the sense of discovery of fictional archaeology.
- Published
- 2017
21. Explaining Archaeological Research with Video Games.The case of Evolving Planet
- Author
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Rubio, Xavier, Caro Saiz, Jorge, Pongiluppi, Guillem H., Laborda Cabo, Guillem, and Ramos García, David
- Subjects
Video games ,Archaeology ,Jocs de simulació ,Videojocs ,Simulation games ,Arqueologia - Abstract
Archaeology has seen a large number of digital innovations during recent decades. Geographical Information Systems, archaeometry, or laser scanning are only some of the methodological advances of the discipline. However, the public image of how archaeology works is roughly the same as it was several years ago. Public fascination with archaeology is built upon a sense of discovery. Fictional works such as Indiana Jones, the Tomb Raider series (Core Design & Crystal Dynamics 1996-2016) or Uncharted series (Naughty Dog 2007-2016) are based on the concept of solving a mystery by unearthing an artefact or a city that has been forgotten for centuries (Meyers Emery & Reinhard 2015). Non-fiction but still popular media producers, such as Time Team or National Geographic, also promote this sense of wonder while emphasizing the rigorous methodology of archaeological research – as distant from these fictional pillagers as can be imagined.
- Published
- 2017
22. Disseny i implementació d'eines de visualització d'una aplicació científica: Cassandra
- Author
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Casanovas Garcia, Josep, Rubio Campillo, Xavier, Laborda Cabo, Guillem, Casanovas Garcia, Josep, Rubio Campillo, Xavier, and Laborda Cabo, Guillem
- Abstract
Cassandra és una eina de visualització basada en OpenGL [25] que serveix per interpretar resultats i patrons de comportament que ens propcorcionen simulacions (d'ambit social principlament) desenvolupades per Pandora, una llibreria creada pel BSC-CASE (Barcelona Supercomputing Center - Computer Applications in Science & Engineering). Cassandra consta de suport GIS (Geographic Information System), d'una alta escalabilitat i, sobre el que ens centrarem en aquest projecte, de l'anàlisi de grans volums de dades.
- Published
- 2013
23. Disseny i implementació d'eines de visualització d'una aplicació científica: Cassandra
- Author
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Laborda Cabo, Guillem, Casanovas Garcia, Josep, and Rubio Campillo, Xavier
- Subjects
Matemàtiques i estadística::Investigació operativa::Simulació [Àrees temàtiques de la UPC] ,Informàtica::Sistemes d'informació [Àrees temàtiques de la UPC] ,Simulació per ordinador ,Sistemes complexos ,Supercomputació ,Complexity Science ,Mineria de dades ,Computer simulation ,Data mining - Abstract
Cassandra és una eina de visualització basada en OpenGL [25] que serveix per interpretar resultats i patrons de comportament que ens propcorcionen simulacions (d'ambit social principlament) desenvolupades per Pandora, una llibreria creada pel BSC-CASE (Barcelona Supercomputing Center - Computer Applications in Science & Engineering). Cassandra consta de suport GIS (Geographic Information System), d'una alta escalabilitat i, sobre el que ens centrarem en aquest projecte, de l'anàlisi de grans volums de dades.
24. Disseny RTL i implementació d'un framebuffer per un processador RISC-V
- Author
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Rodas Quiroga, Narcís, Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya. Departament de Ciències de la Computació, Barcelona Supercomputing Center, Moreto Planas, Miquel, and Cabo, Guillem
- Subjects
Software engineering ,VGA ,RTL ,RISC-V ,AXI ,Verilog ,Arquitectura d'ordinadors ,RISC microprocessors ,Framebuffer ,RISC (Microprocessadors) ,Computer architecture ,Memòria de vídeo ,Enginyeria de programari ,Informàtica::Arquitectura de computadors [Àrees temàtiques de la UPC] - Abstract
El conjunt d'instruccions o ISA (de l'anglès instruction set architecture) RISC-V i la fundació que el recolza segueixen creixent ràpidament com una alternativa open-source per als dissenys hardware. Tot i que el software open-source ja representa una part important de totes les solucions software, el hardware open-source encara està començant a expandir-se. Abans d'això, el mercat estava format íntegrament per ISAs propietàries (la gran majoria provinents dels EUA) que el controlaven. Aquest Treball de Final de Grau mostra el disseny, implementació i el testing d'un framebuffer VGA pel processador RISC-V que s'està desenvolupant en el projecte DRAC del Barcelona Supercomputing Centre. En aquest document s'expliquen els diversos passos seguits i el raonament darrera les decisions preses. The RISC-V instruction set architecture (ISA) and the foundation that supports it continue to grow rapidly as an open-source alternative for hardware designs. Despite open-source software already being established as an important part of all the software solutions, open-source hardware has only recently begun to expand. Before that, the market was entirely made of proprietary ISAs (mostly from the US) that controlled it. This Final Degree Thesis shows the design, implementation and testing of a VGA (Video Graphics Array) framebuffer for the RISC-V processor being developed in the DRAC project by the Barcelona Supercomputing Centre. This document explains the various steps taken along the way and the reasoning behind the decisions that were taken.
- Published
- 2020
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