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CPUs typically operate at a voltage which is higher than what is strictly required, using voltage margins to account for process variability and anticipate any combination of adverse operating conditions. However, these worst-case scenarios occur rarely, if ever, thus the operating voltage is overly pessimistic resulting in excessive power dissipation which leads to decreased performance under power capping. In this paper, we investigate the impact of reducing voltage margins beyond the nominal level on the efficiency of CPU power capping mechanisms, for three commercial systems, two Applied Micro ARMv8 micro-servers (X-Gene2 and X-Gene3) and an Intel x86-64 (Xeon E3). We show that CPU power capping at reduced voltage margins compared with Intel's RAPL and Dynamic Frequency Scaling (DFS) mechanisms results in performance improvement by up to 64% and 24% on average, respectively. In combination with state-of-the-art thread packing, the reduction of CPU voltage margins results in 36%, 33% and 27% performance improvement compared with RAPL and DFS for the Xeon E3 and the X-Gene processors, respectively. Also, we validate the robustness of our approach with a set of long-running experiments and show that significant energy gains can be achieved even when considering the cost of checkpointing and recovery in large-scale systems.

In recent years, DPDK (Data Plane Development Kit, a data plane development tool set provided by Intel, focusing on high-performance processing of data packets in network applications), one of the high-performance packet I/O frameworks, is widely used to improve the efficiency of data transmission in the cluster. But, the busy polling used in DPDK will not only waste a lot of CPU cycles and cause certain power consumption, but also the high CPU usage will have a great impact on the performance of other applications in the host. Although some technologies, such as DVFS (dynamic voltage and frequency scaling, which is to dynamically adjust the operating frequency and voltage of the chip according to the different needs of the computing power of the application running on the chip, so as to achieve the purpose of energy saving) and LPI (low power idle, a technology that saves power by turning off the power of certain supporting circuits when the CPU core is idle), can reduce power consumption by adjusting CPU voltage and frequency, they can also cause performance degradation in other applications. Using thread sleep technology is a promising method to reduce the CPU usage and power consumption. However, it is challenging because the appropriate thread sleep duration cannot be obtained accurately. In this paper, we propose a model that finds the optimal thread sleep duration to solve the above challenges. From the model, we can balance the thread CPU usage and transmission efficiency to obtain the optimal sleep duration called the transmission performance threshold. Experiments show that the proposed models can significantly reduce the thread CPU usage. Generally, while the communication performance is slightly reduced, the CPU utilization is reduced by about 80%.

Dynamic Voltage Scaling is performed on automotive micro-controller AURIX from Infineon Technologies. In this micro-controller the core and different IPs operate on the 1.25 V supply rail, so dynamically voltage is changed according to the workload in the micro-controller. DVS is done either using an internal onboard voltage regulator or an external voltage regulator. An External board (KITPF3000FRDMEV), which has a controller and a Power Management Integrated Circuit (PMIC) is used for changing the supply voltage to the micro-controller during DVS using an external voltage regulator. The micro-controller is predicting the workload and according to workload, the control command is sent to the controller (FRDM-KL25) in the kit through I2C communication and then the controller sends the command to adjust the voltage of PMIC (PF3000) through I2C communication. Both current measurements for the internal voltage regulator and external voltage regulator are measured for various loads and latency is measured for various baud rates while using external voltage regulator through I2C protocol.

This article presents a static random access memory (SRAM)-based flexible radiation monitor. The monitor was fabricated in a 65-nm CMOS technology and it is designed as an application-specific integrated circuit, which comprises 768k bits SRAM cell matrix with individual power supply and a digital control core with a serial peripheral interface (SPI). By adjusting the core voltage of the SRAM matrix, the radiation sensitivity was made flexible. Also, SRAM cells with different threshold voltages were implemented to get further extension on tunable sensitivity range. The monitor has been tested under heavy ions with a linear energy transfer (LET) from 1.5 to 48.5 $\text {MeV}\cdot \text {cm}^{2}$ /mg, high-energy (50–186 MeV) and low-energy (0.7–5 MeV) protons, and 14-MeV and thermal neutrons. An analysis was performed on how single-event upset sensitivity changes while tuning the supply voltage under different radiation environments. The results show that the monitor has the potential for space and facility applications.

DC-to-DC power supplies are critical components for processors in high performance computing and datacenter servers. Conversion from an intermediate bus voltage (e.g., 12 or 48 V) to the core voltage (∼0.9 V) of processors must be efficient, compact, and cost effective. This paper proposes two versions of active-clamp forward converter (ACFC) power blocks to supply core voltage from either 12 or 48 V intermediate bus voltage. The ACFC power block can be individually tested prior to assembly and vertically soldered onto the motherboard to fit in a standard 1U server. A low loss, compact planar transformer is designed into the ACFC power block printed circuit board (PCB). A custom, standing slab inductor not only provides high inductance and high saturation current but also helps to mechanically support the power block. A one-piece copper winding connects the transformer to the inductor, thereby reducing the dc loss in the current path. Thorough analysis is performed to model the conversion loss of the proposed power block. Experimental results show a peak efficiency of 90.4% (12 V input) and 89.5% (48 V input) with 0.9-V output.

This paper presents an alternative method for achieving more efficient and reliable DC-DC conversion and balancing operations for low-power applications in a stacked voltage domain. This work comprehensively analyzes the operating principles and power conversion loss of a proposed capacitor-stacking balancing circuit at the system level. The analysis and design of the capacitor-stacking balancing circuit in the stacked voltage domain, including the time-domain operation, voltage equation, and dead-time effect, are explored and implemented. This study provides an opportunity to achieve a highly optimized system with high efficiency. A comprehensive analysis of efficiency at the system level shows the advantages and limitations according to each stacking method under a given system condition. Considering the redundancy issues of the previous method at system-level analysis, the capacitor-stacking balancing method is a preferable choice for low-power, high-reliability, and high-efficiency applications under light load conditions. This study also provides an analytical efficiency model under current imbalance, which is a notable difference from previous research and case studies concerning power converters. Prototype board with lithium-ion battery power and a core voltage of 0.825 V-a low-power application-was built to verify the proposed model and analysis. The experimental efficiency reached 94.9% at 20% of the maximum workload.

This paper presents a 48 V–1 V merged-two-stage hybrid-switched-capacitor converter with a Linear Extendable Group Operated Point-of-Load (LEGO-PoL) architecture for ultra-high-current microprocessors, featuring 3-D stacked packaging and coupled inductors for miniaturized size and vertical power delivery. The architecture is highly modular and scalable. The switched capacitor circuits are connected in series on the input side to split the high input voltage into multiple stacked voltage domains. The multiphase buck circuits are connected in parallel to distribute the high output current into multiple parallel current paths. It leverages the advantages of switched capacitor circuits and multiphase buck circuits to achieve soft charging, current sharing, and voltage balancing. The inductors of the multiphase buck converters are used as current sources to soft-charge and soft-switch the switched-capacitor circuits, and the switched-capacitor circuits are utilized to ensure current sharing among the multiphase buck circuits. A 780 A vertical stacked CPU voltage regulator with a peak efficiency of 91.1% and a full load efficiency of 79.2% at an output voltage of 1 V with liquid cooling is built and tested. This is the first demonstration of a 48 V–1 V CPU voltage regulator to achieve over 1 A/mm2 current density and the first to achieve 1,000 W/in3 power density. It regulates output voltage between 0.8 V and 1.5 V through the entire 780 A current range.

A 10nm 4-core x86 IP with multiple low-power states including C1 (clock-gated core), C6 (power-gated core) and a new state called C1LP where the core voltage is lowered to its retention voltage (V RETENTION ) is presented. All-digital closed-loop unified retention clamp for C1LP and wake up for C6 shows power savings of 33%/28% for core/IP, with 120ns wake up latency while addressing impact of PVT variations.

Three-dimensional (3D) integration is adopted in the semiconductor industry to overcome the slowdown of Moore’s Law. The 3D integration is beneficial in terms of interconnection bandwidth, wire delay, power efficiency, and area. However, the on-chip temperature of 3D stacked CPUs is known as much higher than that of conventional 2D CPUs due to the higher power density and lower heat dissipation capability. High on-chip temperature leads to performance degradation of 3D stacked CPUs due to following reasons: 1) High on-chip temperature leads to frequent Dynamic Thermal Management (DTM) invocations, which limits practical CPU voltage and clock frequency. 2) The power limits are used to proactively deal with the thermal problems from high on-chip temperature by adjusting the CPU clock frequency. In this paper, we explore the thermal characteristics of the first off-the-shelf through-silicon-via (TSV) based 3D stacked CPU (Intel Lakefield). In our evaluation, 3D CPU w/ the forced air cooling w/o PL1 shows 21.7% and 6% better single thread performance, on average, compared to 3D CPU w/ PL1 and 3D CPU w/o PL1, respectively. Although the 3D stacked CPU was launched to the market, we identify that the thermal problems of the 3D stacked CPU have not been fully resolved. To tackle the thermal problems of 3D stacked CPUs in the future, researchers are required to consider more innovative integration technologies, optimized DTM techniques, and advanced cooling solutions.

This paper performs thorough investigations of very fast transients (VFTs) in a 500 kV gas-insulated substation (GIS) by adopting complete earth-return impedance and admittance formulas. VFT simulations are performed with wideband (WB) models in a simulation tool for electromagnetic transients. The effects of various GIS parameters on VFTs are investigated. The maximum core and pipe voltages along the GIS are presented. The frequency spectra of VFT voltages are evaluated, and the effects of GIS length and transformer capacitances on the VFT frequencies are analyzed. The frequency decreases as the GIS total length increases. The frequency is decreased significantly by stray capacitances of transformers because those are far greater than the GIB capacitance. The effect of pipe grounding on the pipe voltage is very noticeable, but on the core voltage and the oscillating frequency is minor. The position of an operating DS influences the VFT over-voltages and frequency significantly. Approximate analytical formulas are derived for physical and qualitative interpretation of simulation results.

The high penetration levels of distributed generators (DGs), on the one hand, make the operational state of distribution grids increasingly complex; on the other hand, they enrich voltage regulation measures. Consequently, a voltage control strategy of the distribution grid for coordinating DGs and other voltage regulation devices is needed. This paper applies the security region methodology to coordinated voltage control. To meet the demand of online voltage security assessment and control in the distribution grids, a hyperplane expression for the boundary of the static voltage security region (SVSR) in complex power injection spaces is derived, and a corresponding fast generation method is proposed. Additionally, based on SVSR, a two-stage voltage control strategy is proposed. In the first stage, the regulation devices are automatically selected according to the coefficients in the hyperplane expressions, and the regulation effect can be estimated by SVSR. In the second stage, the outputs of the devices are determined by utilizing an optimization technique. The proposed voltage control strategy is tested by using a modified PG&E69-bus distribution grid, and the results verify the effectiveness.

Modern field-programmable gate arrays (FPGAs) operate at a core voltage around 1 V and therefore even small voltage fluctuations lead to timing violations and logic errors. The power delivery network (PDN) between the voltage regulator and the FPGA core must be carefully designed to achieve a low output impedance over a broad range of frequencies. Simulation tools are commonly used to estimate the impedance, however, they do not account for aging, component variations, and inaccurate modeling of parasitic elements, all of which lead to PDN design deviation. In this paper, two schemes are presented: first, to extract the dc resistance in the power delivery path, and second, to identify the high impedance frequency band(s) in the PDN. The embedded impedance extraction tool is synthesized within the FPGA load, in coordination with a mixed-signal current-mode dc–dc converter. A new self-calibrated carry-chain-based analog-to-digital converter (CC-ADC) is used for high-speed sampling of the core voltage. The proposed schemes are demonstrated on an Intel Cyclone IV FPGA board. Real-time IR -drop compensation is shown to eliminate logic errors in an finite impulse response filter application. It is also shown that the fail/pass map of a crossbar application matches well with the extracted impedance profile versus voltage and frequency. By modifying the PDN based on the extracted results, the voltage operating range and reliability of the crossbar application are greatly extended.

Field programmable gate arrays (FPGAs) are widely used in telecom, medical, military, cloud computing, and other high-performance computing applications, thanks to their unique combination of parallel hardware execution and reprogrammability. During compilation, the computer-aided design (CAD) tool estimates the maximum operating frequency of the user application based on the worst case timing analysis of the critical path at a fixed nominal supply voltage, which usually results in significant voltage or frequency margin. Hence dynamic voltage scaling (DVS) has great potential to reduce the power overhead in FPGAs; however, the reprogrammability of FPGAs make a safe implementation of DVS for any application that could be programmed into the FPGA challenging. This work presents a robust universal DVS scheme for FPGAs intended to run on a system production line, or regularly during each FPGA power-up. The proposed scheme requires the FPGA to be programmed twice: offline self-calibration and online DVS. During the offline self-calibration, the FPGA frequency and core voltage operating limits at different self-imposed temperatures are automatically found and stored in a calibration table (CT). During online operation, the power stage refers to the CT and dynamically adjusts the core voltage according to the FPGA temperature and the resistive voltage drop in the power delivery path. The proposed DVS scheme is demonstrated on a 60-nm Intel Cyclone IV FPGA, with a digitally controlled dc–dc converter, leading to 40% power savings in two typical applications.

The paper presents SRAM cache design in 5nm FinFET technology for L2/L3 cache applications, demonstrating circuit techniques to enable wide-range DVFS (Dynamic Voltage and Frequency scaling) operation. CPU L2/L3 SRAM cache must achieve higher density while meeting performance and power criteria defined for each operating performance point (OPP). 6-T High Density (HD) bitcell is the ideal bitcell choice to achieve cache density requirements. However HD bitcell needs write assist to ensure robust write across operating range. In this work an area efficient NBL write assist technique is implemented which deploys a circuit technique to operate boost capacitor at SRAM core voltage domain (Vsram). This NBL technique minimizes voltage variation across boost capacitor and help to address overboost and underboost concerns. A selftime scheme is also introduced in the work which is designed in a way to control selftime window depending on delay tracking from both SRAM core (Vsram) and periphery (Vperi) supplies. The scheme ensures adequate design margins with optimized performance across wide voltage range to satisfy performance and power requirements of CPU DVFS system. The techniques of Selftime tracking and NBL assist have been successfully implemented in a 5nm finfet SRAM testchip. Silicon results show all SRAM instances achieved 100% yield with a robust operating range from 0.45v-1.1v.

This paper proposes a bipolar junction transistor (BJT) based complementary metal-oxide-semiconductor (CMOS) body temperature sensor analog front-end (AFE) with dynamic element matching (DEM). To reduce mismatches of current sources and transistors resulting from process spread, DEM is implemented. A chopper stabilization technique is implemented to minimize input offset at op-amp which forms a feedback loop to generate proportional-to-absolute-temperature (PTAT) currents in the temperature sensor core. The gain stage used to achieve high-resolution output of temperature sensor implements non-inverting amplifier using R-2R digital-to-analog converter (DAC) to perform amplification regardless of the output offset voltage of the temperature sensor core. The proposed temperature sensor is implemented in a $0.18\ \mu\mathrm{m}$ CMOS process, occupies 0.1 mm2, and consumes $4.85\ \mu\mathrm{A}$ from 3.3 V I/O and 1.8 V core voltage.

The paper discusses the microcontroller power supply, which makes it possible to vary the output voltage to provide the required ration between productivity and energy consumption of the device. When the deigned power supply is implemented, the microcontroller core voltage is defined by the fill factor of the PWM module. Equations shown in this work make it possible to adjust the power supply for any modern microcontroller.

Dynamic frequency and voltage scaling features have been introduced to manage ever-growing heat and power consumption in modern processors. Design restrictions ensure frequency and voltage are adjusted as a pair, based on the current load, because for each frequency there is only a certain voltage range where the processor can operate correctly. For this purpose, many processors (including the widespread Intel Core series) expose privileged software interfaces to dynamically regulate processor frequency and operating voltage. In this paper, we demonstrate that these privileged interfaces can be reliably exploited to undermine the system’s security. We present the Plundervolt attack, in which a privileged software adversary abuses an undocumented Intel Core voltage scaling interface to corrupt the integrity of Intel SGX enclave computations. Plundervolt carefully controls the processor’s supply voltage during an enclave computation, inducing predictable faults within the processor package. Consequently, even Intel SGX’s memory encryption/authentication technology cannot protect against Plundervolt. In multiple case studies, we show how the induced faults in enclave computations can be leveraged in real-world attacks to recover keys from cryptographic algorithms (including the AES-NI instruction set extension) or to induce memory safety vulnerabilities into bug-free enclave code. We finally discuss why mitigating Plundervolt is not trivial, requiring trusted computing base recovery through microcode updates or hardware changes.

Transient ionizing radiation produces instantaneous photocurrents which cause current and voltage disturbances in integrated circuits. In this paper, a 0.18μm bulk CMOS inverter chain circuit with core and IO power supplies is investigated by pulsed laser simulated the transient dose rate effects. The experimental results show the disturbance of output voltage is positively correlated with core and IO supply voltages, and more affected by the core voltage. The recovery time of output voltage depends on the recovery time of core power supply. 1.8V and 3.3V inverters with different supply voltages are simulated by Sentaurus TCAD. The results also show the disturbance of output voltage is positively correlated with power supply voltage, and the disturbance of supply voltage corresponds to the disturbance of supply current. It is indicated that power supply is an important factor affecting the transient ionizing radiation effects in integrated circuits.

With reduction in core voltage for digital logic, the design of low voltage (LV) to high voltage (HV) level shifter to support standard input-output interface poses several challenges. The floating and full-scale level shifter are used to convert such LV signals to HV domain without stressing the devices. In this paper we present an adaptive high voltage level shifter which improves the switching speed of circuit with increasing any static current. The proposed circuit is designed on a 28nm FDSOI (Fully Depleted Silicon on Insulators) process and supports upto 200MHz transaction speed at 100fF load. The proposed circuit exhibits less variation across process, voltage and temperature while consuming $3.6\mu \mathrm{W}/\text{MHz}$ typical dynamic power.

Recently, FPGA-accelerated cloud has emerged as a new computing environment. The inclusion of FPGAs in the cloud has created new security risks, some of which are due to circuits exercising excessive switching activity. These power-wasting tenants can cause timing faults in the collocated circuits or a denial-of-service attack by resetting the host FPGA. In this work, we present the idea of populating the FPGA with voltage sensors based on ring oscillators, to continuously monitor the core voltage fluctuations across the entire FPGA. To implement the sensors, we do not lock any FPGA resources; instead, we infiltrate the sensors undercover, by taking advantage of the logic and the routing resources unused by the tenants. Additionally, we infiltrate the sensors into the FPGA circuits after their implementation, but before their deployment on the cloud; the tenants are thus neither aware nor affected by our voltage monitoring system. Finally, we devise a novel metric that takes the sensor measurements to quantify the power wasting activity in the FPGA clock regions where the sensors are infiltrated. We use VTR benchmarks and a Xilinx Virtex-7 FPGA to test the feasibility of our approach. Experimental results demonstrate that, using the undercover voltage sensors and our novel metric, one can accurately locate the source of the malicious power-wasting activity.

The rack-level 48 V bus architecture is wide-spreading as modern Data Center architectures move towards the cloud computing and Internet of Things Era. Increasing power demands require low-profile, high-density server board solutions able to efficiently step down the input distribution bus to the digital rails. Intermediate Bus Converters (IBCs) are usually implemented though soft-switching resonant topologies such as non-regulated LLCs, while core voltage regulation is achieved through a multi-phase buck VRM. This paper proposes two different architectures to increase the power density of the 48 V-1.8 V conversion: the IBC is implemented through a regulated switched-capacitor converter, while the Point-of-Load stage is a novel 4:1 fully-coupled buck that enables DC magnetic flux cancellation and leakage inductance minimization to improve the load transient response.

Integrated circuit (IC) manufacturers perform production tests to detect defective part to guarantee the quality level of the product. Weak ICs contain flaws, defects that do not cause functional failures at some or all normal operating conditions but degrade the ICs performance, reduce noise margins, or draw excessive supply current. The current normal Low voltage test is not able to defect weak ICs or eliminate the early-life failures. The auto and military customers have very high quality requirement. Very-Low-voltage test can detect the defects (flaws) that cause early-life failures or intermittent failures. And the cost of Very-Low-Voltage test is very low. Very-Low-Voltage testing is a method where a test is performed at a supply voltage that is much lower than its nominal operating voltage. It can detect resistive shorts and delay flaws that are caused by degraded signals or diminished-drive gates. It can be implemented in die level, and no special equipment requirement of replacing the defect, which do not bring the additional cost. In this paper, the study aimed mainly at Very-Low-Voltage implemented in DC Scan test at probe level, and the core voltage value of DC scan test for different domains setup is discussed. JMP software is data analysis tool used in the study, including data comparison among DOM1, DOM2, DOM3 and ARM core. Optimized the core voltage, determining the best parameters to be used, and implemented it in probe program. Collected the real probe Very-Low-Voltage rejects and do Electric and Physical Failure Analysis(FA). For the failure unit, diagnostic, shmoo analysis between Level (VDD_SOC_CAP) and Period, Laser Assisted Device Alteration(LADA), and Soft Defect Localization(SDL) were performed on failure unit, and the anomaly was found. After the unit was thinned, Electron-Optical Probing(EOP) and cross section were performed on the anomaly location. The high resistive conduct among metal is found in FA. With the optimized data, the good probe test performance was get, and improved ICs quality. The Very-Low-Voltage test can screen out the normal low voltage rejects. The traditional normal low voltage DC Scan tests were replaced by Very-Low-Voltage DC Scan tests, which also reduce the probe test time. It is concluded that the Very-Low-Voltage test is good test method in probe to guarantee the die quality, improve the defect coverage, screen out the weak ICs, and reduce the test cost.

Due to the difficulty of leakage current separation and cable core voltage acquisition, the traditional high voltage cable online monitoring system of dielectric loss have low precision and data instability. Therefore, a new online monitoring system for high voltage cable dielectric loss has been proposed, the accuracy of dielectric loss detection is improved, and the safe and stable operation of the cable is guaranteed. First, the principle of the high voltage cable dielectric loss detection system is introduced. Then, the influence of the distance between the cabinet and the cable on the accuracy of the dielectric loss is analyzed, and the method of correcting the distance error by the ranging method is proposed. Different cable transmission modes were analyzed for the effect of the sensor for leakage current separation, and a method of installing simultaneous sampling current monitoring units was proposed. Finally, the influence of different sampling errors on the dielectric loss detection results is analyzed, and a method of ensuring sampling synchronization using a satellite synchronization system is proposed. The high-voltage cable dielectric loss online monitoring system proposed in the paper is also applicable to live detection.

The equivalent circuit of self-ice-melting conductor contains large capacitance components and inductance components. When applying alternating current ice-melting power supply, capacitance components and inductance components will consume a large amount of reactive power. In order to avoid reactive power consumption, direct current ice-melting power supply is needed. While the aluminium strand of the self-ice-melting conductor conveys alternating current power, and the steel core voltage is the sum of aluminium strand voltage and a fixed voltage, the voltage difference between the steel core and the aluminium strand will be direct current. The secondary side of alternating current transmission transformer is designed with transmission winding and ice melting winding. The transmission winding is used to generate transmission power and connect to the aluminium strand. Two modular multi-level converters are connected with the ice-melting winding. The first modular multi-level converter converts the output voltage of the ice-melting winding to direct current, and the second modular multi-level converter converts direct current to the sum of the voltage of the aluminum strand and the fixed voltage. By the designed method of this paper, direct current power supply for ice melting can be generated between steel core and aluminium strand to restrain the reactive power consumption.

A novel 79-nW CMOS-only subthreshold voltage reference with 328-mV output voltage, which works down to 0.8-V supply voltage, is presented in this brief. In order to reduce the area and power consumption, the proposed circuit avoids the use of resistors and bipolar transistors. A current subtracting technique is proposed to realize the temperature compensation of reference current. Instead of the op-amp in traditional circuits, some cascode current mirrors are used to enhance the power supply rejection ratio (PSRR). A novel structure consisting of a 1.8-V MOS transistor and a 3.3-V MOS transistor is utilized to accomplish the voltage temperature compensation and to further reduce the power consumption of VREF generator. The proposed voltage reference was fabricated in 0.18- ${\mu }\text{m}$ CMOS process. The measured results show that the temperature coefficient of the output voltage is 33.8 ppm/°C in the range from 10 °C to 100 °C, the PSRR is −55 dB @ 100 Hz at 1.2-V power supply, and the line regulation is 0.21%/V in a supply voltage range of 0.8 to 3.4 V. What is more, the power dissipation is 79 nW, and the chip area is 0.01 mm2. It is suitable for low-power applications.

This paper develops a novel voltage equalizer by combining wireless power transfer (WPT) and a voltage multiplier (VM) for series-connected energy storage cells. The physical isolation achieved by WPT can offer several unique benefits that traditional equalizers can hardly provide. In this paper, the characteristics of a multiple-output VM are analytically discussed and used to develop an equivalent one-output VM model. Based on this model, parameters of the WPT system are properly designed. The proposed design methodology can achieve a single-switch voltage equalizer without feedback control, which dramatically decreases the circuit complexity and cost. Moreover, this methodology can naturally ensure a robust system under small coil misalignment. In the experiment, the proposed system is built to balance four series-connected ultracapacitor modules. The system efficiency is 72.8% at a load power level of 10 W.

With the recent advancements in ultra-low power wireless devices such as wireless sensor networks, the demand for nanowatt voltage references capable of operating below 1-V becomes a necessity. But due to the low voltage overhead imposed by the supply, most of the recent literatures on sub-1-V voltage references exhibited low power supply rejection ratio (PSRR) and thus were prone to switching noise induced at the supply line. This paper presents a high PSRR, subthreshold MOSFET-only voltage reference which has been simulated in $0.18\ \mu\mathrm{m}$ TSMC CMOS process using the Synopsys HSPICE tool. The circuit employed a PSRR enhancement block that suppresses the variation along the supply of the core voltage reference. This circuit block implemented a negative feedback network that regulated the internal supply voltage of the core reference circuit. Simulation results showed that the proposed overall circuit generated an output voltage of 244.5 mV which operated properly at a supply voltage of 0.95-V and achieved a PSRR of −140.6 dB, −101.1 dB, − 64.3 dB, and −38.4 dB at 100 Hz, 1 kHz, 10 kHz, and 10 MHz respectively. The circuit also achieved a temperature coefficient of 9.9 ppm/oC from −25 °C to 100 °C while consuming only 74.6 nW. From these results, the designed high PSRR voltage reference provides the necessary specifications suitable for wireless sensor network nodes.

This work proposes sensing CPU voltage noise through wireless electromagnetic (EM) emanations from the CPU. Compared to previous voltage monitoring methodologies, this approach is not intrusive as it does not require direct physical access to the monitored CPU. To prove the effectiveness of this approach, we use EM signal feedback to find the resonant frequency of the CPU power delivery network, and to generate a CPU voltage noise (dI/dt) virus. This study is performed on a modern out-of-order CPU that supports on-chip fine grain voltage monitoring. This on-chip voltage monitoring capability is used to validate the proposed EM methodology. © 2017 IEEE. 17 1 68 71

In this paper, a method has been proposed by which one can reduce the clock jitter and achieve almost flat frequency clock output from the phase-locked loop (PLL), independent of the power supply voltage fluctuation. These voltage fluctuations occur when a given chip comes out from the sleep mode to the active mode. This causes the chip to draw a hasty current, which in turn produces LdI/dt noise. That causes the voltage to drop and also to oscillate at the power delivery network’s resonance frequency. This power supply noise causes clock jitter. The voltage-controlled oscillator of the proposed PLL is designed at 45-nm technology such that when there is supply voltage variation, it is automatically corrected by a feedback methodology having only 11-ps response time delay, compared to 588-ps clock period. Simulation result shows that, for the proposed new PLL design, the number of places where the clock periods are altered due to this power supply voltage fluctuation is reduced. The performance of the proposed PLL design in terms of reduction of clock jitter, caused by the variation of power supply voltage and the flatness of the frequency versus power supply voltages, is tested by feeding the clock to a circuit (c17 of ISCAS’85) for the conventional methodology and also for our new methodology. It has been shown that, using the proposed method, the clock jitter caused by the power supply noise can be reduced by about 50% compared to the conventional design methodology.

In this paper we present a reliable and efficient SR-Latch based PUF design, with two times improvement in area over the state of the art, thus making it very attractive for low-area designs. This PUF is able to reliably generate a cryptographic key. The PUF response is generated by quantifying the number of oscillations during the metastability state for preselected latches. The derived design has been verified on 25 Xilinx Spartan-6 FPGAs (XC6SLX16) and 10 Xilinx Zynq SoC (XC7Z010) devices. The design exhibited ∼49% uniqueness figures when tested on both types of FPGAs. The reliability figures were >94% for temperature variation (0–85 °C) and ±5% of core voltage variation.

This brief presents a fully integrated cross-coupled voltage multiplier for boosting dc-to-dc converter applications. The proposed design applies a new structure of cross-coupled voltage doubler (CCVD) and a clock scheme that eliminates all of the reversion power loss and increases the power efficiency (PE). In addition, this design is scalable to multiple-stage voltage doubler (voltage multiplier) as the maximum gate-to-source/drain or drain-to-source voltage does not exceed the nominal power supply $V_\mathrm{dd}$ . As a result, such a design is compatible with the standard CMOS process without any overstress voltage. The proposed single-stage CCVD and three-stage cross-coupled voltage multiplier are implemented in 0.13- $\mu\text{m}$ IBM CMOS process with maximum PE values of 88.16% and 80.2%, respectively. The maximum voltage conversion efficiency reaches 99.8% under the supply voltage of 1.2 V.

In this paper, a novel discontinuous current-source driver (CSD) is proposed, in which the power MOSFET gate-source voltage is increased to more than the drive supply voltage. The proposed CSD is able to recover gate energy dissipated in a conventional driver. In comparison to the conventional gate driver, the proposed CSD achieves fast switching speed to reduce switching losses. A wide range of operating duty cycle, low circulating losses, and high Cdv/dt immunity are other features of the proposed CSD. In comparison to previous discontinuous CSDs, the special advantage of the proposed circuit is power MOSFET gate voltage boosting, which leads to reduction of Rds(on) and, thus, the conduction loss. The proposed circuit is appropriate for voltage regulators (VRs) with synchronous rectifier and also it is suitable for two-stage 48-V power pod applications and low-voltage converters. Two-stage VR for laptop computer CPUs is another application of this gate driver circuit to improve light load performance. A prototype of the circuit operating at 1 MHz is implemented, and the experimental waveforms justify the theoretical analysis.

This paper presents a 16-core voltage-stacked system with adaptive frequency clocking (AFClk) and a fully integrated voltage regulator that demonstrates efficient on-chip power delivery for multicore systems. Voltage stacking alleviates power delivery inefficiencies due to off-chip parasitics but adds complexity to combat internal voltage noise. To address the corresponding issue of internal voltage noise, the system utilizes an AFClk scheme with an efficient switched-capacitor dc–dc converter to mitigate noise on the stack layers and to improve system performance and efficiency. Experimental results demonstrate robust voltage noise mitigation as well as the potential of voltage stacking as a highly efficient power delivery scheme. This paper also illustrates that augmenting the hardware techniques with intelligent workload allocation that exploits the inherent properties of voltage stacking can preemptively reduce the interlayer activity mismatch and improve system efficiency.

In recent years, the wide-voltage-operating-range circuit has drawn great attention because of its ad-hoc performance and energy efficiency to meet the demands of various applications. The circuit can either obtain the best possible energy efficiency at low voltage or achieve high performance at nominal voltage. A big challenge is the severe Process, Voltage, and Temperature variations under the nanometer process. Thus, when working at the near-threshold region, it may result in timing failure and fails to achieve the possible high-energy efficiency. In this paper, an Adaptive Voltage Scaling (AVS) method based on in-suit timing monitor is proposed with a tunable detection window. It resolves the above problem by monitoring the paths' timing and adjusts the supply voltage adaptively. It is applied on a system-on-chip circuit consistig of a CPU, ESRAM, an AES cryptographic circuit, and peripherals. Fabricated using the SMIC 40nm CMOS process, it can work at 0.6 to 1.1 V with remarkable power savings. Simulation results show that in the super-threshold voltage region, the supply voltage can be reduced from 1.1 to 0.86 V, enabling a maximum of 50% power saving at the FF corner, -25°C as compared to conventional non-AVS design. In the near-threshold region, the supply voltage is reduced to 0.48 V, with a power saving up to 70% at the FF corner, 125°C as compared to a non-AVS design.

Dynamic Voltage and Frequency Scaling (DVFS) typically adapts CPU power consumption by modifying a processor’s operating frequency (and the associated voltage). Typical DVFS approaches include using default strategies such as running at the lowest or the highest frequency or reacting to the CPU’s runtime load to reduce or increase frequency based on the CPU usage. In this article, we argue that a compile-time approach to CPU frequency selection is achievable for affine program regions and can significantly outperform runtime-based approaches. We first propose a lightweight runtime approach that can exploit the properties of the power profile specific to a processor, outperforming classical Linux governors such as powersave or on-demand for computational kernels. We then demonstrate that, for affine kernels in the application, a purely compile-time approach to CPU frequency and core count selection is achievable, providing significant additional benefits over the runtime approach. Our framework relies on a one-time profiling of the target CPU, along with a compile-time categorization of loop-based code segments in the application. These are combined to determine at compile-time the frequency and the number of cores to use to execute each affine region to optimize energy or energy-delay product. Extensive evaluation on 60 benchmarks and 5 multi-core CPUs show that our approach systematically outperforms the powersave Linux governor while also improving overall performance.

This paper presents a novel methodology for on-chip power-noise modeling in the early stage of system-on-chip (SoC) design. Conventionally, the on-chip power-noise simulation is performed in “placement and routing” design stage. Therefore, designers experience difficulty in applying the simulation results to improve power-noise performance because of the delivery time. The proposed methodology enables modeling of the dynamic current profile, without any geometry information and estimation of SoC power noise in the register-transfer-level design phase. Each SoC sub-block is defined as a unit simplified chip power model (SCPM), and the defined unit SCPMs are integrated into one SCPM, including multiblock characteristics. SCPM presents various types of current profiles to accurately predict the maximum current peak, and it includes the background current to prevent overestimation of the ac current. To improve the simulation accuracy, this paper proposes a voltage ripple measurement method that considers the SoC operating scenario. The simulation results of the SCPM are verified by the measurement results, and the SCPM methodology shows the correlation results of 7 and 18 mV on two test vehicles with a 1.1 V core voltage. In the chip-package design industry for electronic applications, the proposed methodology presents a design guide for the power delivery network, such as essential capacitance per location (e.g., chip, package, and printed circuit board) and the limit of the off-chip routing inductance. In addition, the forecast by the SCPM simulation shows that preactive design is available at the early stages of the design process.

This work represents a high resolution and low jitter 5-bit Flash Time to Digital converter (TDC) which concurrently achieves low power and improved periodic jitter. To minimize quantization error τQ and attain high resolution, equally spaced flash TDC is calibrated with least mean square algorithm (LMS). The adaptive filtration minimizes the error which minimizes the delay variation among the delay cells of flash TDC. Further slow and accurate 5 bit SAR TDC is used to calibrate the proposed TDC. The implementation of TDC is done in 0.18um digital CMOS logic technology. The results show the resolution of measurement is 6 ps. The dynamic power consumption is 1.98 mW at 25 °C temperature and 1.8 V core voltage.

Electronic speed controller (ESC) is an important subsystem in drones, which are used to control and regulate the speed of its electric motor. For the high-end drones which require longer flight times, higher dynamic behavior with smooth and stable performance, Field Oriented Controllers (FOC) which power three-phase sinusoidal back-EMF motors are typically used to provide the required high efficiency, small torque ripple and dynamic performance. This paper proposes an analysis method based on discrete Fourier transform (DFT) over the measured motor current, in order to optimize the system parameters such as modulation period, CPU clock frequency and power supply voltage. As proof of concept, a FOC-based ESC implemented in a generic 32-bit microcontroller is studied. Findings show that the power quality and motor dynamic performance of a FOC ESC depends strongly on modulation period and relatively insensitive with respect to CPU voltage and frequency scaling.

Embedded computing systems are becoming increasingly complex, now performing tasks that were generally limited to desktop computing systems. However, embedded system designers are still required to adhere to stringent embedded design constraints (e.g., energy and area requirements) when designing such increasingly complex systems. To meet these constraints, configurable hardware components introduce configurable parameters (e.g., CPU voltage and frequency, cache size, cache associativity, cache line size, pipeline depth/width, etc.) that can be tuned to specific values to meet different design constraints (e.g., area, energy, performance, etc.) and user demands (e.g., increased battery life, increased performance, or a desired trade off), which translates to a better quality of the user experience. However, determining these specific parameter values is increasingly difficult and time-consuming as the configurable parameter design space increases. This issue is further complicated when considering that each application has a different set of optimal/best parameter values based on these demands and requirements. Furthermore, repetitious application behavior, known as phases, which occur throughout an application's runtime, can be exploited by tracking each phase's unique optimal parameter values; resulting in a multiplicative increase or an exponential increase in the size of the size of the configuration space. In this paper, we propose a machine learning-based methodology to significantly reduce the time required to find the optimal configurable parameter values for the instruction and data caches for each application phase. In our method, we use artificial neural networks (ANNs) to predict the optimal configuration for application phases. We collect execution statistics for use as features for an application phase and use feature reduction to significantly reduce the features size. We show that ANNs exhibit high, stable accuracy over multiple training and testing iterations. We also show that applications exhibit low energy degradations (less than 1%) for both the instruction and data caches using our methodology.

This paper investigates the core voltage’s reduction of electronics induced by transient ionizing radiation and how it influences TREE (Transient Ionizing Radiation Effect of Electronics) on SRAM. 6T memory cell of 40nm SRAM was constructed in TCAD and the dose-rate upset threshold of it was 1.5×1011Gy(Si)/s when working at nominal core voltage. However, the transient ionizing radiation experiment of 40nm SRAM carried out on “QiangGuang-I” accelerator indicated that the dose-rate upset threshold of the whole SRAM chip was1.0×107 Gy(Si)/s. And the simulation results indicated that the reduction of memory cell’s core voltage would reduce the dose-rate upset threshold significantly as the memory cell’s SNM (Static Noise Margin) decreases with the reduction of memory cell’s core voltage. As there is LDO (Low Dropout Regulator) inside SRAM for conversion of voltage from I/O to core, we also did the transient ionizing radiation experiment of LDO and the experimental results showed that the output voltage of LDO would decrease during transient ionizing radiation which verified the probability of the reduction of memory cell’s core voltage during transient ionizing radiation. Combined with the experiment and simulation results, it can be assumed that the reduction of core voltage during radiation is a main reason causing SRAM upset.

Energy efficiency is a major concern for cloud computing, with CPUs accounting a significant fraction of datacenter nodes power consumption. CPU manufacturers introduce voltage margins to guarantee correct operation. However, these are unnecessarily wide for real-world execution scenarios, and translate to increased power consumption. In this paper, we investigate how such margins can be exploited by infrastructure operators, by selectively undervolting nodes, at the controlled risk of inducing failures and activating service-level agreement (SLA) violation penalties. We model the problem in a formal way, capturing the most important aspects that drive VM management and system configuration decisions. Then, we introduce XM-VFS policy that reduces infrastructure operator costs by reducing voltage margins, and compare it with the state-of-the-art which employs dynamic voltage-frequency scaling (DVFS) and workload consolidation. We perform simulations to quantify the cost reduction, considering the energy consumption and potential SLA violations. Our results show significant gains, up to 17.35% and 16.32% for the energy and cost reduction respectively. In our simulations, we use realistic assumptions for voltage margins, energy consumption and performance degradation of applications due to frequency scaling, based on the characterization of commercial Intel-and ARM-based machines. Our model and scheduling policy are generic and scalable.

Cryptocurrency mining with GPUs for profit has a fine edge of finding the best rate for mining power versus energy consumption. In this research we explore different GPU settings, namely memory clock and core voltage influence on mining performance measured as hash rate. Additionally, we look for opportunities to lower power consumption. Experiment using combined power of five commonly available graphics cards showed improvement of hash rate with increased memory clock frequencies, and lower power consumption with decreased core voltages. However, these dependencies are not linear, and some other factors, like different memory chips on otherwise similar graphics card models may give contradicting results.

The energy for data transfer has an increasingeffect on the total system energy as technology scales, oftenovertaking computation energy. To reduce the power of interchipinterconnects, an adaptive encoding scheme called AdaptiveWord Reordering (AWR) is proposed that effectively decreasesthe number of signal transitions, leading to a significant powerreduction. AWR outperforms other adaptive encoding schemesin terms of decrease in transitions, yielding up to 73% reductionin switching. Furthermore, complex bit transition computationsare represented as delays in the time domain to limit thepower overhead due to encoding. The saved power outweighs theoverhead beyond a moderate wire length where the I/O voltageis assumed equal to the core voltage. For a typical I/O voltage,the decrease in power is significant reaching 23% at just 1 mm.

This development of smart dental unit is the collaboration between College of Biomedical Engineering, Rangsit University and C.C. AUTOPART Co., Ltd. The purpose of this project is to develop the smart dental unit system to obtain product certification for Thai Industrial Standard and reduce the import of medical instruments from foreign country. The development process started from review, the research prototype development and efficiency improvement that comply with the Thai Industrial Standard. In this study, the research team focused on the technical development process and the functional corrections of the dental unit system in order to obtain the test results conform with laboratory standards, which consists of two main components as follows: (1) Structure of dental chair have made from cast iron that can be operated by using PIC18F26K22 microcontroller and (2) Online monitoring and notification system which are; Water Pressure System in the range of 2–8 Bar, Main Air Pressure in the range of 4–12 Bar, Air Pressure of Dental Bur in the range of 2–6 Bar, Core Voltage in the range of 184–240 VAC., Hydraulic system which has 100–300 mA., Solenoid Valve which active in the range of 100–300 mA., Electric Current of Dental Lamp which has range between 100–300 mA, Oil level (HL) and Safety Switch can save the data to the server at a prescribed period of time from 1 to 30 minutes. The preliminary test results of both parts were established from the NECTEC and PTEC labs, respectively. The results show that they are in accordance with TIS 2610-2556 and the prototype has the potential to a commercial product in near future.

Neural network models show promising speed and accuracy for online and on-site data analysis in high energy physics. In this report, we discuss a multi-functional neural computing chip called PulseDL for measurement of pulse characteristics. We adopted a structure with outside RISC CPU and processing engines in PulseDL for balanced power and performance. Digital logic at register transfer level was specially designed with emphasis on thread level parallelism. Based on the hardware scheme, we co-designed the network architecture to best utilize the on-chip resources. Convolution, deconvolution and fully-connected matrix multiplication of the network were fitted into the hardware with reconfiguration during runtime. The chip has been taped out under the GSMCR013 130 nm process, with 4.9 mm × 4.9 mm area, at least 25 MHz working frequency and 1.2 V core voltage. Measured by post-layout simulations, the peak power efficiency of the chip was estimated to be about 12 giga operations per second per watt.

Dynamic power management for mobile processors has become very important due to the increased clock speed and number of cores. There have been various power management governors using dynamic voltage and frequency scaling (DVFS). Among them, a user-centric power management has received a lot of attention as a method to save power while maintaining the quality of user experience (UX) referring to the perceived quality of system services to end users. Most user-centric governors have employed DVFS as a method to reduce the power consumption. However, DVFS may not be adequate enough to guarantee UX qualities for all task because the CPU clock speed changed by DVFS can affect all tasks running at the same processor. In order to minimize such inter-task interferences by DVFS, it is necessary to employ task-specific power management methods. This paper shows that CPU bandwidth control developed for CPU resource management within Linux kernel can be employed as a task-specific power management method, and a novel CPU power management scheme employing both DVFS and CPU bandwidth control is proposed. Experimental results show that the proposed governor can reduce the power consumption more than the Ondemand governor can achieve while maintaining the quality of UX.

This paper presents four topologies of voltage-mode un-terminated IO cells in 28-nm CMOS for single-ended rail-to-rail signaling over a passive interposer die in 2.5D configuration for >1Gbps data rates. The presented design explores the existing IO design-space from a 2.5D viewpoint, optimizing existing topologies from area, speed, power and protection perspectives, with a higher degree of configurability in the form of pre-emphasis and slew-rate control. The transmitter TX embeds pre-emphasis to enhance high-frequency components of the signal for longer low-pass natured channels. The TX also implements slew-rate control to minimize reflections on shorter channels because of impedance discontinuities and also to minimize simultaneous switching noise. Level-shifting capability embedded in the receiver RX enables multi-technology interfacing where different dies are signaling at their core voltages range: 0.7V-1.8V instead of following a particular signaling standard. The measurement results of the transceivers, over a interposer of length of 3.5mm, demonstrate ±5% duty-cycle distortion with 700µW at 500MHz/0.8-V-signaling on the channel with jitter of 20ps, ±10% duty-cycle distortion with 1.8mW at 1Gbps/0.9-V signaling with jitter of 20ps, ±10% duty-cycle distortion with 2mW at 2Gbps/0.7-V signaling for 1-V receiver core voltage with a jitter of 10ps. Copyright © 2016 John Wiley & Sons, Ltd.

This work presents a detailed methodology to design a precision voltage reference circuit using MOSFET devices. First, the I–V relations of saturation and subthreshold MOSFETs are presented along with the temperature dependency of these devices. Then, a step-by-step procedure on how to design the main building blocks of voltage reference circuits is discussed. The proper relations between these building blocks are detailed. Moreover, circuit techniques to minimize the impact of process, voltage and temperature (PVT) variations on the voltage reference circuit are introduced. In order to verify the methodological approach, a novel circuit is presented. This new design has been simulated in the state-of-the-art 28 nm CMOS technology using Synopsys Custom Designer and HSPICE CAD tools. It generates a reference voltage of 252 mV with line sensitivity (LS) of 0.64% in a supply voltage range of 0.85–4.1 V. The temperature coefficient (TC) is 218.8 ppm/°C, through a temperature range of −15–80 °C. The power supply rejection ratio (PSRR) is −34 dB at 50 Hz and −48.6 dB at 1 MHz. Finally, the power consumption is 395 nW at nominal supply voltage. The process variations coefficient is 0.19%, and the peak-to-peak output noise is 3.08 μV/(Hz)1/2 at 10 Hz.