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This paper addresses the challenge of efficiently designing multiplexer structures in quantum-dot technology circuits. Specifically, it introduces a novel approach to constructing a 2-to-1 multiplexer through a unique gate design that relies on the interaction between cells. The key focus of this design is to minimize the utilization of cells, thereby conserving space and facilitating the creation of more complex combinational and sequential circuits. The methodology involves developing a gate structure that requires the least number of cells compared to existing designs. This reduction in cell usage not only optimizes space utilization but also enhances the scalability of the multiplexer for integration into larger circuits. The proposed gate structure demonstrates a significant improvement, achieving a 15% reduction in the number of cells compared to the previously best-known design. To further evaluate the effectiveness of this novel gate design, the study extends its analysis to include the implementation of various complex circuits such as a 4-to-1 multiplexer, D latch, and T latch. These structures are synthesized using the newly proposed gate design as a fundamental building block. To validate the functionality and performance of these circuits, simulations are conducted using the QCADesigner simulation tool. This comprehensive simulation enables a thorough assessment of the proposed structures across different circuit configurations, providing insights into their operational efficiency and suitability for practical applications in quantum-dot technology. [ABSTRACT FROM AUTHOR]

Summary Digital MemComputing machines (DMMs), which employ nonlinear dynamical systems with memory (time non‐locality), have proven to be a robust and scalable unconventional computing approach for solving a wide variety of combinatorial optimization problems. However, most of the research so far has focused on the numerical simulations of the equations of motion of DMMs. This inevitably subjects time to discretization, which brings its own (numerical) issues that would be otherwise absent in actual physical systems operating in continuous time. Although hardware realizations of DMMs have been previously suggested, their implementation would require materials and devices that are not so easy to integrate with traditional electronics. Addressing this, our study introduces a novel hardware design for DMMs, utilizing readily available electronic components. This approach not only significantly boosts computational speed compared to current models but also exhibits remarkable robustness against additive noise. Crucially, it circumvents the limitations imposed by numerical noise, ensuring enhanced stability and reliability during extended operations. This paves a new path for tackling increasingly complex problems, leveraging the inherent advantages of DMMs in a more practical and accessible framework. [ABSTRACT FROM AUTHOR]

This paper presents the design of a synergistic arithmetic logic unit (SALU) that combines a complementary metal-oxide–semiconductor (CMOS) and memristors using the modified gate diffusion input (m_GDI) technique. The proposed design aims to reduce power consumption, delay, and the number of transistors, which are critical parameters in digital VLSI design. We have incorporated the m_GDI technique to implement the SALU, resulting in a lower number of transistors and reduced power consumption along with the delay and power delay product (PDP). The whole proposed architecture has been constructed using a basic m_GDI cell that consists of one p-type (pMOS) and two memristors. Combinational arithmetic circuits like full adder and full subtractor have been designed using the XOR-based m_GDI approach, and their performance will double that of current methods. A 1-to-8 de multiplexer circuit has also been utilized to perform 8 different operations for the ALU. Using Cadence Virtuoso tools in 45-nm technology, we have simulated the proposed design and evaluated its performance with existing designs. The proposed design has the potential to be a viable option for low-power and high-performance digital VLSI design applications. It delivers improved power, delay, and PDP characteristics while using fewer components. The power consumption, delay, and PDP of the proposed architecture are 9.71E−6 W, 2.141E−9 s, and 2.0789E−14 J, respectively. Furthermore, the design comprises just 33 pMOS transistors and 66 memristors, which is a lower count and unique combination in contrast to previous techniques. [ABSTRACT FROM AUTHOR]

This paper studies the fault propagation and the correctness rate calculation of combinatorial circuits. We rely on circuit partitioning and on a probabilistic approach close to a binomial distribution, assuming some simultaneous faults have a certain probability to occur in the circuit's gates. We extend the results of our Clusterized Probabilistic Binomial Reliability model (CPBR), in which we obtained the results for several combinatorial multiplier designs, as seen in our previous publication. We now target non-arithmetic combinatorial netlists and, among them, a few circuits with flip-flop instances. We use the graph representation of the combinatorial netlists and we generalize our approach with a generic algorithm for CPBR. To develop this algorithm, we use some existing work on multilevel acyclic hypergraph partitioning, that we adapt to acyclic directed graphs. Furthermore, we address the problem of calculating correctness rates of circuits in cases where sequential flip-flops induce cycles in the graph. Our experiments show that our approach is capable of analysing the error and the correctness rates of significant non-arithmetic circuits, with an automatized and generic tool. [ABSTRACT FROM AUTHOR]

Functional circuits are a group of combinational logic circuits which may be utilized for certain tasks and with specific planning. Decoders, multiplexers, and demultiplexers are all functional circuits that come in useful when creating complex systems. Quantum-dot cellular automata (QCA) is a flourishing technology that would be so practical in the field of computational digital circuits in terms of its advantages such as low energy consumption. This paper proposes various quaternary 1:4 decoders (enabling decoder, active-high and active-low decoders). Then, 4:1 multiplexer and 1:4 demultiplexer were architectured using the proposed 1:4 decoder. In the following, a quaternary to the binary converter (a 4-valued digit to a 2-bits circuit) is designed regarding the validated proposed structures. All designs were simulated and verified by QCASim. The total area used for the decoder, multiplexer, demultiplexer, and quaternary to the binary converter are 0.01, 0.19, 0.03, 0.13 μm2. The complexity and delay are 30, 387, 88, 214 and 0.5, 3.25, 1, 2 respectively. This work gets compared to CMOS and carbon nanotube field-effect transistor articles. Furthermore, the proposed 4:1 quaternary QCA multiplexer got compared with the binary QCA multiplexers. The comparison results show that our proposed designs are efficient in terms of having a low delay, area, and complexity. [ABSTRACT FROM AUTHOR]

A dual band L-shaped patch antenna with a defected ground structure is designed and tested for wireless communication applications like ISM and sub-6GHz. Excitation of the antenna is given through a 50O feed line. Concentric circular rings with different radius have been subtracted from the ground plane to attain better results in terms of return loss, gain and wider bandwidth. Parametric analysis of the antenna is done by using HFSS, chemical etching has been utilized to fabricate the antenna and the antenna is tested by utilizing MS2037C Anritsu combinational Analyser. The Lshaped microstrip patch antenna exhibits dual band characteristics at 2.3GHz-2.6GHz and 3.7GHz-3.8GHz with S11 of -30dB and -38 dB with a gain of 4.61dBi. The overall size of the antenna is 1.20λ0X1.20λ0X0.21λ0 and to validate the antenna, it is fabricated by using Rogers/RT duroid 5880 the simulated results are in good agreement with the measured antennas results and it is well suited for ISM band as well as for sub-6GHz applications. [ABSTRACT FROM AUTHOR]

Clock attacks and power attacks are used as common means to inject faults in embedded devices. Critical analysis of the properties and the components engaged with these fault injection methods is of high importance to assess the related dangers and furthermore to enhance the process of designing suitable counter-measures. This paper provides critical analysis of induced faults on combinational and sequential circuits and study effects of various attacks (over-clock, under clock, power attack). While doing analysis, it was revealed that clock attacks i.e., under and over clock attacks have similarity index of (80–90%). Also it was found that power attacks have results similar (60–70%) to clock attacks but they cause propagation delay in circuits affecting the output. Cadence virtuoso 45 nm technology node, Keil and Multi-sim software's were used to generate various attacks. The comparative analysis reveals that the attack timing and frequency of the glitch is the key while inducing fault injection attacks. While performing this work, it is observed the sequential circuits get less impacted by attacks comparing to combinational circuits. This research is conducted from an attacker's perspective instead of mitigation perspective. [ABSTRACT FROM AUTHOR]

Logical gates have been used in implementation of logic sequential and combinational circuits especially in computers, DSPs and microprocessors. They are mostly fabricated based on CMOS technology that provides a few nano-seconds of delay for each digital gate. Due to limitations in more scaling CMOS transistors and cause of short channel effects, some engineers and researchers believe that there is a huge demand for new devices and fabrication technologies to produce faster logic gates. In this paper, a new architecture for NAND gate is presented which operates based on mechanical resonance of a network of weakly coupled resonators that resonate in radio frequencies. This design is achieved by employing the associative memory property of Hopfield neural networks and the theory of weakly coupled resonators. The main advantage of the proposed design is in its capability to reach out delay times of the order of 1 nano-seconds or even less. One solution to decrease the delay time can be increasing the resonance frequency of resonators which are processing elements of resonators network. In this paper just the new idea of implementation NAND gate based on weakly coupled RF MEMS resonators is presented and evaluated. Other criteria like gate power consumption, effects of temperature, fan in, fan out and noise margin are not discussed. Regarding the rapid growth in MEMS technology, resonators with super high frequency (SHF 3–30 GHz) are now available and those with Extremely High frequency (EHF 30–300 GHz) will soon be in market which enables the presented design to achieve higher speeds. In addition, mechanical resonators are more fault tolerant than CMOS circuits when utilized in harsh environments which exposed to ionic beams or electron beam radiations. In space applications, the satellite and payload are exposed to huge bombardments of space electrons and ions beams. So, the proposed NAND gate can be a good solution for enhancing reliability of devices and systems exposed to space radiations. [ABSTRACT FROM AUTHOR]

A parity generator as a combinational logic circuit in digital circuits can generate the parity bit in the transmitter. It is very applicable in digital networking and communications. Also, rather than diodes and transistors, quantum dots will be used in the next-generation circuits. Quantum-dot Cellular Automata (QCA) offers a new platform where binary data is represented by polarized cells that are defined by the electron configurations. Therefore, a coplanar 4-bit parity generator is suggested in this work. This new arrangement eliminates complicated crossovers and provides complete access to all input and output pins. An XOR gate is used to implement the suggested architecture. Simulation waveforms and performance data confirm the proposed circuits' functioning and advantages. The suggested four-bit parity generator uses less overhead than its equivalents. We simulated and tested the suggested circuit with the assistance of the QCADesigner 2.0.3 simulator. The QCADesigner software findings demonstrate that the suggested design is simpler and less expensive than earlier designs. Compared to the present best design, the suggested four-bit parity generator reduces cell number and latency by 55.29% and 40%, respectively. Quantum dot-Cellular Automata (QCA) offers a new platform where binary data is represented by polarized cells that are defined by the electron configurations. Therefore, a coplanar 4-bit parity generator is suggested in this work. This new arrangement eliminates complicated crossovers and provides complete access to all input and output pins. An XOR gate is used to implement the suggested architecture. Simulation waveforms and performance data confirm the proposed circuits' functioning and advantages. The suggested four-bit parity generator uses less overhead than its equivalents. We simulated and tested the suggested circuit with the assistance of the QCADesigner 2.0.3 simulator. The QCADesigner software findings demonstrate that the suggested design is simpler and less expensive than earlier designs. Compared to the present best design, the suggested four-bit parity generator reduces cell number and latency by 55.29% and 40%, respectively. [ABSTRACT FROM AUTHOR]

Silicon waveguides are essential to integrated photonics, which is where optical and electronic components are coupled together on a single silicon chip. These waveguides allow for the integration of signal processing and optical transmission, which advances data centers, telecommunications, and other optical applications. Thus, our study involves the simulation of essential all-optical logic operations, namely XOR, AND, OR, NOT, NOR, NAND, and XNOR, and utilizes M-shaped silicon optical waveguides at a wavelength of 1.55 μm. This simulation is conducted through Lumerical FDTD solutions. The suggested waveguide comprises four identical slots, configured in the shape of the letter 'M', and all of which are formed of core silicon and silica cladding. These logic operations work based on constructive and destructive interferences that are caused by phase changes in the input optical beams. The contrast ratio (CR) is employed to quantitatively and comparatively assess the degree to which the target logic operations are efficiently executed. The simulation results indicate that, compared to other reported designs, the considered logic functions constructed using the proposed waveguide can be implemented with higher CRs. The outcomes of this paper can be utilized regarding the implementation of optoelectronic combinational logic circuits of enhanced functionality. [ABSTRACT FROM AUTHOR]

In the wireless communication technologies of today are used to transfer enormous amounts of digital data frequently between various embedded devices. For avoiding information loss and stopping cybercrimes, data security is regarded as a crucial factor. Modern cryptography encryption techniques are essential for creating secure communication. The Advanced Encryption Standard (AES) is widely regarded as the cryptography field's strongest encryption technique. In AES has three types of keys using that is AES128, AES192, AES256 and blocksize only 128bits. In this paper using AES-256, because it's very secure for valuable information. This research paper describes how the AES algorithm uses a low area, little latency, high-speed FPGA design to secure data. The implementation of the SubBytes and InvSubBytes phases of AES encryption and decryption in this research did not rely on Look-Up Tables (LUTs). Instead, this novel approach employed combinational logical circuits to construct the SubBytes and InvSubBytes transformation. Here analysed AES Logic gates approach reduced area in terms of number of slices LUTs are 6120, slice registers are 226, flip flops are 6120, and bonded IOB are 513 when compared to the LUT. Unwanted delays in this design are reduced because of the removal of LUTs, and a Three Stage pipelining structure is added to enhance the performance of the AES algorithm. AES Logic gates three stage pipeline approach reduced delay up to 60.55ns when compared to Logic gates without pipeline approach. The proposed approach simulated, synthesized Implemented with Virtex-5 FPGA device along with design in Verilog code in XILINX 14.7 Software. [ABSTRACT FROM AUTHOR]

This paper presents the review of recent progress in photonic crystal fiber (PCF) and its applications. PCF possesses prominent potential for demonstrating various optical devices such as logic gates, combinational circuits, sensors, absorbers, etc. Recent development in PCFs incorporates the deep learning algorithms which deploy new functionalities and enhance the performance capacity in term of accuracy and optimization in comparison to conventional techniques based on Maxwell solver like finite element method (FEM), and plane wave expansion and finite difference time domain (FDTD) method. Thus, this review paper describes the overview of recent development along with historical background of PCFs and rigorous study on deep learning which incorporates neural network and machine learning algorithms like polynomial expansion method, gradient boost, and random forest. [ABSTRACT FROM AUTHOR]

In this work, bottom‐up Al–Si–Al nanowire (NW) heterostructures are presented, which act as a prototype vehicle toward top‐down fabricated nanosheet (NS) and multi‐wire (MW) reconfigurable field‐effect transistors (RFETs). Evaluating the key parameters of these transistors regarding the on‐ and off‐currents as well as threshold voltages for n‐ and p‐type operation exhibit a high degree of symmetry. Most notably also a low device‐to‐device variability is achieved. In this respect, the investigated Al–Si material system reveals its relevance for reconfigurable logic cells obtained from Si NSs. To show the versatility of the proposed devices, this work reports on a combinational wired‐AND gate obtained from a multi‐gate RFET. Additionally, up‐scaling the current is achieved by realizing a MW RFET without compromising reconfigurability. The Al–Si–Al platform has substantial potential to enable complex adaptive and self‐learning combinational and sequential circuits with energy efficient and small footprint computing paradigms as well as for native components for hardware security circuits. [ABSTRACT FROM AUTHOR]

This paper presents the realization of binary and floating-point comparators on FPGA. The implementation is done by exploiting the primitive instantiation of FPGA resources which has enabled a significant improvement in resource utilization in terms of Look-Up Table (LUT) usage and overall combinational path delay when compared to the conventional inference approach. The comparator architectures are implemented using Vivado 2020.1 and ISE Design Suite 14.7 environment on multiple Xilinx FPGA platforms and are compared with the existing designs. The results indicate an improvement of 33.33% and 45.45% in LUT utilization, 14.41% and 30.73% in delay for 32-bit and 64-bit binary comparators respectively, compared to the existing architectures. The proposed floating-point comparator requires 88.57% and 285.29% lesser LUTs for single precision and double precision representation respectively, compared to the existing design. [ABSTRACT FROM AUTHOR]

This work proposes a frequency‐selective surface‐based radome structure to selectively allow the radar altimeter operating band and also minimize the interference from Sub‐6GHz 5 G frequency bands. A Jerusalem cross and combinational loop (JCL) based frequency selective surfaces (FSS) unit cell of overall dimension 0.37λ was synthesized using a thin flexible substrate for use in fuselage of airborne systems. The proposed FSS unit cell exhibits transmission zero at 3.61 and 6.025 GHz and highly selective pass band at 4.3 GHz. The effect of bends and angle of incidence on the frequency response of the synthesized FSS was studied in transverse electric and transverse magnetic modes. A lumped element‐based equivalent circuit model for the proposed design was also presented. Finally, the fabricated prototype was experimentally validated in an Anechoic chamber setup and the suitability of the proposed FSS layers for aviation radar systems was confirmed. [ABSTRACT FROM AUTHOR]

Considering that the traditional investment project evaluation system can no longer fully adapt to the characteristics of the new power system under the investment environment of the new power system, this study constructed a new power system investment project evaluation and optimization method based on the combination of the cloud model, evidence theory and the TOPSIS method. First, 16 evaluation indexes were considered based on four dimensions, namely green and low‐carbon, safe and reliable, flexible and intelligent, and economical and efficient, and the optimal evaluation index system of new power system investment projects was designed. Second, the normal cloud model was used to obtain the evaluation membership distribution of each index and turn it into evidence. Considering the conflicts between indicators and the combinational contradictions of traditional evidence theories, an improved DS evidence theory based on a game weight coefficient discount to reduce conflicting evidence was used to fuse the membership information of multiple indicators. On the basis of the evaluation results of each scheme, this study used the TOPSIS method to sort the advantages and disadvantages of each scheme. Finally, the project of planning and putting this model into operation in the 14th Five‐Year project database of a power grid enterprise was selected as an example to carry out empirical analysis, and the effectiveness and superiority of the proposed model were verified. [ABSTRACT FROM AUTHOR]

Classical combinational logic circuits (CCLCs) are widely used in various fields. Corresponding to the CCLCs, here schemes are given for some quantum combinational logic circuits (QCLCs) based on the quantum NAND tree. Three typical circuits, adder, comparator, and seven‐segment display decoder, are discussed in detail as examples. All the designs of the schemes are based on the quantum random walk theory. Furthermore, these QCLCs are mapped onto the classical circuit networks and design new types of CCLCs, and take advantage of the fact that there is a good correspondence between the voltage in the circuit satisfying Kirchhoff's law and the system wave function satisfying the Schrodinger equation. These CCLCs that are designed have exponential speedup functions compared with conventional ones, which have been demonstrated experimentally. Because classical circuit networks possess good scalability and stability, the realization of QCLCs on classical circuits is expected to have potential applications for information processing in the era of big data. [ABSTRACT FROM AUTHOR]

The multiplexer is a combinational circuit that transfers multiple data inputs over a single output line. The input data are selected and transferred to the output line based on the selection line. In this work, 2 × 1 and 4 × 1 multiplexer is proposed. The proposed multiplexer has been worked out using the electro-optic principle. It is implemented using lithium niobate-based Mach–Zehnder interferometer (LN-MZI). LN-MZI is used as an optical switching device. The performance parameters extinction ratio, contrast ratio and insertion loss have been computed and found 31.31, 28.02 and 0.043 dB respectively. [ABSTRACT FROM AUTHOR]

Nowadays to process information on high speed and to reduce the complexity of digital devices, optical digital computational techniques are required. Many complex signal processing functions such as multiplexing, optical switching, addressing, coding/decoding are implemented using optical digital computational techniques. Optical logic gates are one of the most essential computational elements to design combinational and sequential circuits in optical signal processing. In this paper, all optical logic gates are designed with optimized structure of 2 × 2 Mach–Zehnder interferometer optical switch using Ti:LiNbO3 based waveguide at 1.46 µm employing electro-optic effect. Different design structures to realize all-optical logic gates are presented and compared with the previously designed optical logic gates. The mathematical description of all optical logic gates using cascaded structure of Mach–Zehnder interferometer switch is also defined. The performance parameters of designed optical logic gates have been analyzed by beam propagation method and the obtained results are verified by MATLAB. [ABSTRACT FROM AUTHOR]

This paper proposes an automated framework for test generation for digital circuits, using evolutionary algorithms (EAs) such as Genetic Algorithm (GA) and Particle Swarm Optimization (PSO) targeting single stuck-at faults. The framework is built in MATLAB environment in conjunction with an open-source fault simulator HOPE. Finding the best test pattern with maximum fault coverage from a very large search space of digital tests is proven to be time effective in VLSI circuits using EAs. This work emphasizes upon finding the best test pattern with maximum fault coverage in fewer iterations. This indeed can significantly reduce the number of required test patterns to achieve a good fault coverage quickly. Unlike open source ATPG tool ATALANTA which can generate tests only for combinational circuits, our EA based test generation framework is able to generate test pattern for combinational as well as sequential circuits. The proposed framework has introduced test generation for sequential circuits before and after their "netlist cutting". In this context, an automated tool which can perform "netlist cutting" for sequential circuits without altering the structure of combinational logic has been devised. The quality of generated test patterns is verified through fault simulation of some of the ISCAS'85 combinational and ISCAS'89 sequential benchmark circuits. The work has also explored the efficacy of the best test pattern through variations of genetic operators like crossover and mutation rate. Results show that the proposed GA and PSO outperforms the commonly known open source ATPG tool ATALANTA. [ABSTRACT FROM AUTHOR]

Stochastic circuits are used in applications that require low area and power consumption. The computing performed using these circuits is referred to as Stochastic computing (SC). The arithmetic operations in this computing can be realized using minimum logic circuits. The SC system allows a tradeoff of computational accuracy and area; thereby, the challenge in SC is improving the accuracy. The accuracy depends on the SC system's stochastic number generator (SNG) part. SNGs provide the appropriate stochastic input required for stochastic computation. Hence we explore the accuracy in SC for various arithmetic operations performed using stochastic computing with the help of logic circuits. The contributions in this paper are; first, we have performed stochastic computing for arithmetic components using two different SNGs. The SNGs considered are Linear Feed-back Shift Register (LFSR) -based traditional stochastic number generators and S-box-based stochastic number generators. Second, the arithmetic components are implemented in a combinational circuit for algebraic expression in the stochastic domain using two different SNGs. Third, computational analysis for stochastic arithmetic components and the stochastic algebraic equation has been conducted. Finally, accuracy analysis and measurement are performed between LFSR-based computation and S-box-based computation. The novel aspect of this work is the use of S-box-based SNG in the development of stochastic computing in arithmetic components. Also, the implementation of stochastic computing in the combinational circuit using the developed basic arithmetic components, and exploration of accuracy with respect to stochastic number generators used is presented. [ABSTRACT FROM AUTHOR]

The optimization of the number of transistors of combinational logic circuits can lead to faster and cheaper electronic devices, but it is an NP-complete problem. There are deterministic algorithms for this task, but their effectiveness is limited to small problems. Thus, the use of metaheuristics is suitable and Cartesian Genetic Programming (CGP) is widely adopted in the literature. In CGP, mutation is commonly the only operator used for generating new candidate solutions. As a result, the performance of this metaheuristic is dependent on the proper choice of mutation and its parameters. CGP mutation is usually based on uniform mutation and, thus, any modification has the same chance to occur. In order to improve the performance of CGP, a study of the mutation operator is carried out and an adaptive approach using an ϵ -greedy strategy for bias the selection of the node mutation type is proposed here. The proposal is evaluated using a benchmark from the literature. The results obtained indicate that the proposed adaptive mutation is promising, achieving the best mean results in 19 out of the 23 benchmark problems considered here. We also verified a better ability in generating feasible solutions than the standard CGP. [ABSTRACT FROM AUTHOR]

In this work, a novel structure of a double-gate MOSFET is proposed and simulated. The CMOS inverter action in a single device realized by combining p-mode and n-mode MOS transistors is presented. The main advantage of the proposed device is fewer transistors for implementing sequential and combinational circuits. The significant reduction of the transistors, while designing a combinational circuit, will enhance the electronic industry with less power consumption. In our proposed device, a single substrate is used in comparison to the conventional CMOS inverter. The proposed device reduces short channel effects at lesser channel length. For Lg= 50nm, the proposed device, as an inverter, offers a unique VTC curve, SNM, V-curve along with sound values of performance parameters individually for p-mode and n-mode. A significant reduction in the junctions, wells and oxide regions can be seen from the proposed inverter design. Besides the performance of the device, the fabrication steps and the layout of the DGMOSFET-I are also presented in work. [ABSTRACT FROM AUTHOR]

This paper proposes a unique memristor-based design scheme for a balanced ternary digital logic circuit. First, a design method of a single-variable logic function circuit is proposed. Then, by combining with a balanced ternary multiplexer, some common application-type combinational logic circuits are proposed, including a balanced ternary half adder, multiplier and numerical comparator. The above circuits are all simulated and verified in LTSpice, which demonstrate the feasibility of the proposed scheme. [ABSTRACT FROM AUTHOR]

The main purpose of this study is to design combinational logic gates based on a novel configuration of insulator–metal–insulator (IMI) nanoring plasmonic waveguides. Plasmonic logic gates are half adder, full adder, half subtractor, full subtractor, and one-bit comparator and are realized in one structure. The performance of the logic circuits is based on constructive and destructive interferences between the input and control signals. The transmission threshold value is assumed to be 0.35 at the resonance wavelength of 1.310 μm. The transmission spectrum, contrast loss (CL), insertion loss (IL), modulation depth (MD), and contrast ratio (CR) are calculated in order to evaluate the structure's performance. The maximum transmission of the proposed structure is 232% for full a adder logic gate, and MD exceeds 90% in all plasmonic combinational logic circuits. The suggested design plays a key role in the photonic circuits and nanocircuits for all-optical systems and optical communication systems. The combinational logic gates are analyzed and simulated using the finite element method (FEM). [ABSTRACT FROM AUTHOR]

All-optical processor capable of processing optical bits has been a long-standing goal of photonics. In this paper, we report the results obtained by numerical simulations regarding the designing of an all-optical combinational circuit of an adder and subtractor circuits based on Si3N4 microring resonators. The designs of combinational circuit like adders and subtractor based on the use of all-optical basic logic gates are discussed while presenting the numerically simulated results. Extinction ratios of 5.2 dB, 3.5 dB and 2.7 dB are obtained for the half adder, full adder and half subtractor, respectively. [ABSTRACT FROM AUTHOR]

A new learning machine based on neural network (NN) and its hardware accelerator are successfully built in this study for predicting the luminance decay of Organic Light Emitting Diode (OLED) displays. It is known that although OLED displays has become the mainstream in the current high-end display market, OLEDs tend to degrade in emission as used extensively for a long time. The operable voltage also rises with the usage time increasing, which causes the operating point to drift. To compensate the OLED degradation, a NN model is successfully built with favorable accuracy. Furthermore, the built NN model is implemented in FPGA hardware platform with a high-performance computing architecture, which uses registers to access inputs, integrates the multiplication, addition operations for weights and activation function into the same combinational logic circuit, and a pipeline architecture to improve maximum operation per unit time. The hardware architecture is designed via Verilog, and further verified by Xilinx Artix-7. Its operating frequency can be as high as 55.6 MHz, while resource consumption is only 1.0k LUTs, favorable as opposed to all the other past, related studies. Experiment shows that the computation of the built NN by the proposed accelerator can be completed 55.6 million times per second. In addition, the degradation prediction errors by the accelerator are as small as 2.08%, 5.51% and 4.36% for red, green and blue OLEDs, respectively, while the figure of merit, the product of computation time and area is as low as 109.86 (Time*Area), the lowest compared to all the past reported works. [ABSTRACT FROM AUTHOR]

The problems of synthesis of combinational circuits of code converters designed to reduce the length of words from a given set of encoded binary words is considered. The encoding assumes that different binary words will be encoded by different binary codes of shorter length. Code converters of this type are designed to reduce the length of binary words transmitted in digital systems over data buses when the bit depth of the transmitted words exceeds the bit depth of the data bus. For example, 18-bit or 17-bit words need to be transmitted over a 16-bit data bus. Each such word can be transmitted in two cycles of operation of a digital system; however, this approach reduces the overall performance of the system. One of the approaches to solve such problems is the development of combinational circuits that convert long binary encoded words into shorter ones. The proposed methods for solving the problem of synthesizing circuits of code converters are based on the compilation and logical minimization of such forms of systems of incompletely specified Boolean functions as disjunctive normal forms (DNFs) and binary decision diagrams called BDD representations. Using BDDs to minimize representations of k-valued functions that depend on Boolean variables is also proposed. Technology-independent logical minimization of functional descriptions of the designed code converters is proposed to be performed by programs for minimizing the systems of Boolean functions in the DNF class and programs for joint minimization of BDD representations of systems of completely specified Boolean functions. Minimization of functional descriptions is aimed at reducing the hardware complexity of combinational circuits in the basis of library elements or FPGA elements implementing code converters of the class in question. [ABSTRACT FROM AUTHOR]

Grammatical Evolution is a Genetic Programming variant which evolves problems in any arbitrary language that is BNF compliant. Since its inception, Grammatical Evolution has been used to solve real-world problems in different domains such as bio-informatics, architecture design, financial modelling, music, software testing, game artificial intelligence and parallel programming. Multi-output problems deal with predicting numerous output variables simultaneously, a notoriously difficult problem. We present a Multi-Genome Grammatical Evolution better suited for tackling multi-output problems, specifically digital circuits. The Multi-Genome consists of multiple genomes, each evolving a solution to a single unique output variable. Each genome is mapped to create its executable object. The mapping mechanism, genetic, selection, and replacement operators have been adapted to make them well-suited for the Multi-Genome representation and the implementation of a new wrapping operator. Additionally, custom grammar syntax rules and a cyclic dependency-checking algorithm have been presented to facilitate the evolution of inter-output dependencies which may exist in multi-output problems. Multi-Genome Grammatical Evolution is tested on combinational digital circuit benchmark problems. Results show Multi-Genome Grammatical Evolution performs significantly better than standard Grammatical Evolution on these benchmark problems. [ABSTRACT FROM AUTHOR]

This paper presents the development and usage of a web application for troubleshooting logical circuits. The application is designed to support the teaching and learning of troubleshooting logical circuits by providing students with a platform to practice troubleshooting and allowing teachers to monitor students' progress. The web application features an interactive interface that allows students to simulate and troubleshoot logical circuits using the method of truth table. The application also provides students with immediate feedback on their troubleshooting attempts and highlights areas that need improvement. Furthermore, the application has a tracking system that allows instructors to monitor students' progress and identify areas where students may need additional support. Growing complexity and usage of logical combinational circuits require better methods for teaching and improving students' engagement. [ABSTRACT FROM AUTHOR]

Reducing power consumption is a major challenge in developing integrated processors for smart portable devices. This is particularly important for extending battery life and ensuring extended usage of the device. However, some DSP processing applications involve complex algorithms that consume more power, which poses a significant challenge in designing DSP applications for VLSI circuits. To address this issue, low-power consumption methodologies are required. Although various strategies have been developed to reduce power consumption, they have not demonstrated a significant decrease in dynamic power consumption, which is the primary factor determining the total amount of power dissipation. The focus of this research is to develop a low-power multiplier using the spurious power suppression technique (SPST), a method that divides the arithmetic unit into the most significant part (MSP) and least significant part (LSP) and turns off the MSP when it is not required for computation. This approach reduces dynamic power and overall power consumption of the VLSI combinational circuit. The proposed system also utilizes canonical signed digit (CSD) representation to further reduce power usage. The system was designed using Cadence design suite, and the results showed a significant reduction of 35.8% in power consumption for a 32-bit SPST-enabled CSD multiplier. The proposed system's total power consumption is 0.561 mW. Additionally, the proposed system was used in a power and area-efficient 256-point FFT architecture, resulting in an 86.6% reduction in power consumption. This system is suitable for real-time applications such as systems that use orthogonal frequency division multiplexing. [ABSTRACT FROM AUTHOR]

Embryonic architecture that carries self-evolving design with fault tolerant feature is proposed for deep space missions. Fault tolerance is achieved in the embryonic architecture due to its homogeneous structure. The cloning of configuration data or genome data to all the embryonic cells makes each cell capable of selecting required cell function using selective gene. The primary digital circuits of avionics are implemented on the fabric, where the configuration data in Cartesian Genetic Programming (CGP) format is evolved through customized GA. The CGP format is preferred over LUT format for the circuit configuration data due to its fixed data size in case of modular design. Further the CGP format enables fault detection at embryonic cell level as well as logic gate level. The various combinational and sequential circuits like adder, comparator, multiplier, register and counter are designed and implemented on embryonic fabric using Verilog. The circuit performance is evaluated using simulation. The proposed PHsClone genetic algorithm (GA) design with parallel-pipeline approach is to achieve faster convergence. Four concurrent PHsClone GA executions (four parallel threads) achieve convergence for the 10 times faster for a 1-bit adder, and 3 times faster for a 2-bit comparator. [ABSTRACT FROM AUTHOR]

The MapReduce framework has firmly established itself as one of the most widely used parallel computing platforms for processing big data on tera- and peta-byte scale. Approaching it from a theoretical standpoint has proved to be notoriously difficult, however. In continuation of Goodrich et al.'s early efforts, explicitly espousing the goal of putting the MapReduce framework on footing equal to that of long-established models such as the PRAM, we investigate the obvious complexity question of how the computational power of MapReduce algorithms compares to that of combinational Boolean circuits commonly used for parallel computations. Relying on the standard MapReduce model introduced by Karloff et al. a decade ago, we develop an intricate simulation technique to show that any problem in NC (i.e., a problem solved by a logspace-uniform family of Boolean circuits of polynomial size and a depth polylogarithmic in the input size) can be solved by a MapReduce computation in O (T (n) / log ⁡ n) rounds, where n is the input size and T (n) is the depth of the witnessing circuit family. Thus, we are able to closely relate the standard, uniform N C hierarchy modeling parallel computations to the deterministic MapReduce hierarchy D M R C by proving that N C i + 1 ⊆ D M R C i for all i ∈ N. Besides the theoretical significance, this result has important applied aspects as well. In particular, we show for all problems in N C 1 —many practically relevant ones, such as integer multiplication and division, the parity function, and recognizing balanced strings of parentheses being among these—how to solve them in a constant number of deterministic MapReduce rounds. [ABSTRACT FROM AUTHOR]

Low power demand of electronics industry and communication systems are driven by technology scaling and marketing. Compressors are the most often used modules in the architecture of an Arithmetic Circuits. Compressor is the basic combinational digital logic circuit for performing numerous arithmetic operations. The design criterion in any Compressor circuit involves the XOR-XNOR and multiplexer circuits. It is a prominent component in the designing of integrated circuit that performs arithmetic operations. The proposed Compressor is design in order to reduce the transistor count which results in curtailing power dissipation and delay. The performance parameter are recorded and tabulated. This compressor has less delay and low power dissipation. The temperature effect has also shown a linear change in power dissipation in lower temperature ranges which shows the robustness of the proposed circuits. The proposed compressor can be used in numerous applications such as multiplier, DSP microprocessor and data processing systems. [ABSTRACT FROM AUTHOR]

Interconnected cells, Configurable Logic Blocks (CLBs), and input/output (I/O) pads are all present in every Field Programmable Gate Array (FPGA) structure. The interconnects are formed by the physical paths for connecting the blocks. The combinational and sequential circuits are used in the logic blocks to execute logical functions. The FPGA includes two different tests called interconnect testing and logical testing. Instead of using an additional circuitry, the Built-in-Self-Test (BIST) logic is coded into an FPGA, which is then reconfigured to perform its specific operation after the testing is completed. As a result, additional test circuits for the FPGA board are no longer required. The FPGA BIST has no area overhead or performance reduction issues like conventional BIST. A resource-efficient testing scheme is essential to assure the appropriate operation of FPGA look-up tables for effectively testing the functional operation. In this work, the Configurable Logic Blocks (CLBs) of virtex-ultrascale FPGAs are tested using a BIST with a simple architecture. To evaluate the CLBs' capabilities including distributed modes of operation of Random Access Memory (RAM), several types of configurations are created. These setups have the ability to identify 100% stuck-at failures in every CLB. This method is suitable for all phases of FPGA testing and has no overhead or performance cost. [ABSTRACT FROM AUTHOR]

This work applies concepts from algorithmic probability to Boolean and quantum combinatorial logic circuits. The relations among the statistical, algorithmic, computational, and circuit complexities of states are reviewed. Thereafter, the probability of states in the circuit model of computation is defined. Classical and quantum gate sets are compared to select some characteristic sets. The reachability and expressibility in a space-time-bounded setting for these gate sets are enumerated and visualized. These results are studied in terms of computational resources, universality, and quantum behavior. The article suggests how applications like geometric quantum machine learning, novel quantum algorithm synthesis, and quantum artificial general intelligence can benefit by studying circuit probabilities. [ABSTRACT FROM AUTHOR]

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In concurrent online BIST, testing is conducted simultaneously during normal functional operation. A fault model enables a structural test to be undertaken for a long time while simultaneously identifying critical faults. As a result of continuous testing, intermittent and transient faults are more likely to be detected. The number of required cycles for completion of a concurrent test, known as concurrent test latency (CTL), is a critical parameter for a concurrent BIST design. Most of the existing methods have impractical CTL, while others suffer from a high hardware overhead or a presence of a substantial combinational circuit. These methods are also incompatible with situations where parameters need to be adjusted, like when the hardware is more critical than CTL and vice versa. This paper proposes an efficient concurrent BIST to overcome the mentioned challenges. The main components of the proposed design consist of LFSRs and a small decoding combinational module result in low hardware overhead. In addition, CTL and hardware overhead can be adjusted and tuned in an acceptable range using the proposed method. Compared to the most efficient method, the proposed method achieves a 10% reduction in hardware overhead for large-scale circuits by keeping the CTL minimum. The different experiments demonstrate the capability of tuning between CTL and hardware overhead for the proposed BIST design. In the case that CTL and hardware overhead are equally important, the proposed method significantly lowers CTL compared to previous methods, while hardware overhead is only about 4% higher than previous method for both large scale (LS) and very large scale (VLS) circuits. [ABSTRACT FROM AUTHOR]

Metabolic syndrome (MetS) is a non-communicable disease characterized by a cluster of metabolic irregularities. Alarmingly, the prevalence of MetS in people living with Human Immunodeficiency Virus (HIV) and antiretroviral (ARV) usage is increasing rapidly. Insulin resistance is a common characteristic of MetS that leads to the development of Type 2 diabetes mellitus (T2DM). The progression of insulin resistance is strongly linked to inflammasome activation. This study aimed to draw links between the combinational use of Tenofovir disoproxil fumarate (TDF), Lamivudine (3TC), and Dolutegravir (DTG), and inflammasome activation and subsequent promotion of insulin resistance following a 120 h treatment period in HepG2 liver in vitro cell model. Furthermore, we assess microRNA (miR-128a) expression as a negative regulator of the IRS1/AKT signaling pathway. The relative expression of phosphorylated IRS1 was determined by Western blot. Transcript levels of NLRP3, IL-1β, JNK, IRS1, AKT, PI3K, and miR-128a were assessed using quantitative PCR (qPCR). Caspase-1 activity was measured using luminometry. Following exposure to ARVs for 120 h, NLRP3 mRNA expression (p = 0.0500) and caspase-1 activity (p < 0.0001) significantly increased. This was followed by a significant elevation in IL-1β in mRNA expression (p = 0.0015). Additionally, JNK expression (p = 0.0093) was upregulated with coinciding increases in p-IRS1 protein expression (p < 0.0001) and decreased IRS1 mRNA expression (p = 0.0004). Consequently, decreased AKT (p = 0.0005) and PI3K expressions (p = 0.0007) were observed. Interestingly miR-128a expression was significantly upregulated. The results indicate that combinational use of ARVs upregulates inflammasome activation and promotes insulin resistance through dysregulation of the IRS1/PI3K/AKT insulin signaling pathway. [ABSTRACT FROM AUTHOR]

Computer-added design of single-electron nanoelectronic circuits on quantum majority components has been implemented. Proposed methods of building logic-arithmetic computing devices of the combinational type, which implement an almost complete system of logical functions in both the majority and Boolean bases. Quantum cellular automata is a technology that emerged two decades ago, in which the values of logical states correspond to the positions of individual electrons. Quantum cells are used to construct logic nanoelements and arithmetic nanodevices. The work is dedicated to the computer design of modern logic and arithmetic devices, which include universal majority elements. In the work, quantum nano-devices are modeled using QCADesiner automated design system. [ABSTRACT FROM AUTHOR]

The necessity of designing quantum circuits has increased with the development of effective quantum algorithms and methodological developments. The two major outcome that is always desired to achieve in designing a quantum circuit are to reduce the number of gates and also of gate levels. Owing to special features of quantum decoherence, a decrease in gate count and the number of circuit levels minimizes errors which is reflected by probability measurement of output for pre-defined input set. The present paper deals with novel half adder and full adder circuits implemented using CNOT and CCNOT quantum gates. Probabilistic analysis is carried out for each specific case, and result exhibits significant improvement over less area consumption compared to published findings. Results are significant for developing complex combinational circuits using CNOT and CCNOT gates. [ABSTRACT FROM AUTHOR]

This article presents a synthesis strategy aimed at minimizing the dynamic power consumption of combinational circuits mapped in LUT blocks of FPGAs. The implemented circuits represent the mapping of multi-output functions. Properly selected multi-output functions are described using a new form of the binary decision diagram (BDD), which is an extension of pseudomulti-terminal BDDs (PMTBDDs) in the literature. The essence of limiting power consumption is to include additional parameters during decomposition, such as the switching activity associated with the switching PMTBDD (SWPMTBDD). In addition, we highlight the key importance of circuit optimization methods via non-disjoint decomposition when minimizing power consumption. An algorithm is proposed to assess the effectiveness of decomposition, considering several parameters, such as the number of non-disjoint decompositions as well as that of shared and non-shared bound functions or the switching activity. The results of experiments that demonstrate the effectiveness of the proposed methods are also included. [ABSTRACT FROM AUTHOR]

Power optimization can reduce heat dissipation costs and has become an important step of circuit logic synthesis. Because the power optimization for mixed polarity Reed–Muller (MPRM) circuits is a combinatorial optimization problem, in this paper, we first propose a multilevel adaptive memetic algorithm (MAMA), which includes global exploration optimizer, local heuristic optimizer, and initial population optimizer. We use the proposed differential evolution optimization, simulated annealing optimization, and data matching algorithm to make the population evolve. Moreover, based on the proposed matrix decomposition strategy and parallel polarity conversion algorithm, we propose a power optimization approach (POA) for MPRM circuits, which searches for an MPRM circuit with a minimum power using the MAMA. Experimental results demonstrated the effectiveness and superiority of the POA in optimizing the power of MPRM circuits. [ABSTRACT FROM AUTHOR]